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Multiplexed-synchronous-asynchronous-data-bus

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Details

Inventors: Wilson, Gregory P.; Potratz, Bryan A.; Walczak, Thomas J.; Mullins, Jeffery L.; Prill, Mark E.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Safourek; Benedict V.
Assistant Examiner: Bocure; Tesfaldet
Attorney, Agent or Firm: Jenski; Raymond A., Hackbart; Rolland R.

A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.

DETAILED DESCRIPTION Thus, one object of the present invention is to advantageously combine a self-clocking synchronous data bus and a serial asynchronous data bus.
A master data device, which uses a three line transmission bus to convey a first message at one rate of data transfer and to convey a second message at another rate of data transfer, applies a predetermined binary state to two lines of the three line bus when the first message is not being transmitted.
The second message is transmitted on the third line of the three line bus while the other two lines have the predetermined binary states applied.
A data message returned from another data device is detected by the master data device from the third line.

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