RF receiver having improved signal-to-noise ratio and method of operation

DETAILED DESCRIPTION To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a CDMA receiver, a noise reduction circuit for improving a signal-to-noise ratio of a received signal comprising a series of chip sequences.
In an advantageous embodiment, the noise reduction circuit comprises: 1) a sampling circuit for generating an original plurality of samples of the received signal; and 2) a controller capable of determining a first plurality of time slots, each of the first plurality of time slots comprising a plurality of chip samples corresponding to Logic 1, and a second plurality of time slots, each of the second plurality of time slots comprising a plurality of chip samples corresponding to Logic 0, wherein the controller is capable of generating a reconstructed plurality of samples by at least one of: a) modifying an order of a first Logic 1 chip sample and a second Logic 1 chip sample; and b) modifying an order of a first Logic 0 chip sample and a second Logic 0 chip sample.
CDMA provides the foundation for the present invention since the coding and spreading sequence (i.
e.
, chip sequence per bit) are known by both the transmitter and receiver.
In one embodiment of the present invention, the controller adds the reconstructed plurality of samples and the original plurality of samples to generate a composite signal having a reduced signal-to-noise ratio.
The controller uses a correlator or matched filter to de-spread the received signal and the composite signal.
If the matched filter or correlator output does not indicate a signal match with the desired code, the controller generates a new pseudo-signal, sums it with the previously generated pseudo-signal sum and repeats the de-spreading function.
The process repeats until the correlator output indicates a signal match with a signal-to-noise ration (E.
sub.
b/N.
sub.
o) greater that a prescribed threshold or until the execution of a set number of cycles.
This process performs coherent combination of the samples that represent the digital data signal states since the signal states are the amplitude +a (for a chip state of Logic 1) and the amplitude -a (for a chip state of Logic 0)