DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a VLIW processor according to the invention. The processor has an IIR 201 with m issue slots, S. sub. 0, S. sub. 1, . . . , S. sub. m, where m is an integer greater than one. Each slot is for holding an operation to be performed on the functional units. As before, all the operations which are held simultaneously in the IIR are to be begun in a same machine cycle and all of the operations are RISC-like. As before, there is a multiport register file 202. This file has the same number, m, of read ports, RP. sub. 0, RP. sub. 1, . . . , RP. sub. m, as there are issue slots. This file has k write ports where k may or may not be the same as m. More information about multiport register files can be found in U. S. patent application Ser. No. 08/366,958 filed Dec. 30, 1994, which is incorporated herein by reference, though the term read port as used herein includes any operand or guard bit read ports, as those terms are defined in U. S. patent application Ser. No. 08/366,958, filed on Dec. 30, 1994, now abandoned, necessary for execution of an operation. Each read port has a respective group of at least one functional unit which reads from that port. For instance, the drawing illustrates functional units FU. sub. 00, FU. sub. 01, . . . , FU. sub. 0N. sbsb. 0 that read from RP. sub. 0 ; functional units FU. sub. 01, FU. sub. 11, . . . , FU. sub. 1N. sbsb. 1 that read from RP. sub. 1 ; and function units FU. sub. m0, FU. sub. m1, . . . , FU. sub. mN. sbsb. m that read from RP. sub. m. Write buses, 205, 206, . . . , 207, 208, 209, . . . , 210, . . . , 211, 212, . . . , 213, convey result data from the functional units to write control unit 203. Write control unit 203, as in U. S. patent application Ser. No. 08/445,963, determines when to route result data from the write buses to the multiport register file 202 and onto which write ports to route result data. In a sample VLIW processor with m=5 and 19 total functional units, a full read crossbar requires 95 connections. Each connection requires a set of two 32 bit read buses, i
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