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| Method and system for asymmetrically maintaining system operability |
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| Method and system for monitoring computer networks and equipment |
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| Nested measurement period switch algorithm for flow control of available bit rate ATM communications |
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| Managing switched virtual circuits in a network |
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| Packet network performance management |
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| Method and apparatus for increasing the speed of the detecting of computer viruses |
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| Event triggered iterative virus detection |
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Semiconductor integrated circuit with low-power bus structure and system for composing low-power bus structure
| Details |
Inventors: Usami, Kimiyoshi;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Etienne; Ario
Assistant Examiner:
Attorney, Agent or Firm: Foley & Lardner
A bus (9) is structured to reduce Dower consumption. The bus (9) is used to transfer data among functional blocks (1, 3, 5, 7) formed on an LSI chip. The bus is divided into subsections (9a, 9b, 9c). A pair of the functional blocks (1, 7) whose frequency of mutual data transfer is high is connected to the same subsection (9b). Connectors (29, 31) are inserted between the subsections so that the subsections may optionally electrically be connected to and disconnected from each other. When data is transferred between the functional blocks whose frequency of mutual data transfer is high, the subsection to which the functional blocks in question are connected is electrically disconnected by the connectors from the other subsections. |
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DETAILED DESCRIPTION An object of the present invention is to provide a low-power bus structure capable of reducing power consumption.
In order to accomplish the object, the present invention provides a bus structure shown in FIG.
2.
Functional blocks 1, 3, 5, and 7 are arranged on an LSI chip and are connected to a bus 9, which transfers data among the functional blocks.
The bus 9 is divided into subsections 9a, 9b, and 9c.
A pair of the functional blocks, for example, 1 and 7 that frequently transfer data between them is connected to the same subsection, for example, 9b.
The subsections are provided with bidirectional bus drivers 29 and 31 to selectively electrically connect and disconnect the subsections.
If the frequency of mutual data transfer is high between a give pair of the functional blocks, the present invention transfers data between such functional data blocks after electrically disconnecting the subsection to which these functional blocks are connected from the other subsections with the use of the bidirectional bus drivers.
As a result, only part of the parasitic capacitance of the whole bus is charged and discharged at this time.
Compared with the prior art that always charges and discharges the entire parasitic capacitance of the bus, the present invention is capable of reducing the parasitic capacitance that is charged and discharged actually, to decrease total power consumption.
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