Serial access semiconductor memory having a reduced number of data registers

DETAILED DESCRIPTION Accordingly, it is an object of the present invention to provide a serial access semiconductor memory which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a serial access semiconductor memory having data registers of the necessary and sufficient number which is smaller than the number of sense amplifiers in the memory cell array, but capable of ensuring a smooth data transfer in the serial input/output operation comparable to that of the conventional serial access semiconductor memory.
Still another object of the present invention is to provide a serial access semiconductor memory capable of rationally locating sense amplifiers and data registers even if the degree of microminiaturization in the memory cell and the degree of microminiaturization in peripheral circuits including the data buffers are different, to the effect that the data transfer in the serial input/output operation can be smoothly performed similarly to the conventional serial access semiconductor memory.
The above and other objects of the present invention are achieved in accordance with the present invention by a serial access semiconductor memory comprising: a memory cell array having a number of complementary bit line pairs, each of complementary bit line pairs being coupled to a sense amplifier so that a potential difference in the complementary bit line pair is amplified by the sense amplifier; a plurality of data registers each of which is connected to each "m" complementary bit line pairs of the memory cell array through corresponding "m" transfer gates, which are controlled by "m" different data transfer control signal lines, respectively, so that the "m" complementary bit line pairs are sequentially connected to the one data register one at a time, by sequentially activating the "" different data transfer control signal lines one at a time, where "m" is a positive integer not less than 2, and a serial data input/output signal line pair connected in common to all of the data registers so that data held in the data registers can be serially outputted from the respective data registers through the serial data input/output signal line pair by sequentially activating the data registers one at a time