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Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer systems
Under the present invention, the desired results are advantageously achieved by providing the cache controller of a hybrid write back/write through cache of an ...
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Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory
It is an object of the present invention to provide a cache memory control method which is suitable for all kinds of software architectures. It is another object of the ...
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Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization
It is therefore one object of the present invention to provide enhanced data coherency in a data processing system. It is another object of the present invention to ...
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Dynamic mechanism to upgrade o state memory-consistent cache lines
In view of the above and other shortcomings in the art recognized by the present invention, the present invention introduces an O cache consistency state that permits ...
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Non-volatile semiconductor memory capable of readily erasing data
Therefore, one object of the present invention is to provide a non-volatile semiconductor memory in which the area occupied by one memory cell can be reduced. Another ...
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Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
Embodiments of the present invention provide a main memory device and a process for maintaining, in a computer system, a consistent, periodically-updated, checkpoint ...
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Interrupts between asynchronously operating CPUs in fault tolerant computer system
In accordance with one embodiment of the invention, a computer system employs three identical CPUs typically executing the same instruction stream, and has two identical,...
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Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching
In accordance with the present invention, memory accesses are reordered to improve efficiency. A memory controller is used to arbitrate memory access requests from a ...
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Method and apparatus for snoop stretching using signals that convey snoop results
The present invention provides a protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus ...
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