Synchronous clock regenerator for binary serial data signals

DETAILED DESCRIPTION In accordance with the present invention, the incoming raw clock signal with arbitrary phase is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal.
The raw clock signal and the multiple delayed clock signals are connected as inputs to a multiple position latch which is strobed upon detection of a framing transition on the associated incoming data line.
The data stored in the multiple position latch (which represents characteristics of the raw clock signal) is used as the address input to a read only memory (ROM), each word of the ROM containing user determined data specifying which one of the set of multiple delayed versions and the raw timing signal provide optimum phase to strobe the data on the associated incoming data line.
The data output of the ROM is fed into a latch/decoder which is strobed after allowing sufficient time for the data read from the ROM to become valid.
The latch/decoder decodes the bit pattern of the data read from the ROM to determine if any of the set of multiple delayed clock signals and the raw timing signal is suitable as a clock for the incoming data.
If none is suitable, the latch/decoder transmits an unacceptable clock status signal to the associated controlling logic.
Alternately, the latch/decoder provides selection inputs to a 1-of-(n+1) selector, the data inputs to the 1-of-(n+1) selector consisting of the set of multiple delayed clock signals and the raw timing signal.
Thereafter, and until the next unmasked framing transition occurs, each raw clock pulse received is replaced by the corresponding one of the set of that raw clock pulse and the generated delayed versions of that raw clock pulse as selected by the previously latched inputs to the 1-of-(n+1) selector.
Optionally, the present clock regeneration circuit may include an equalizing delay in the associated incoming data line to compensate for the delay introduced by the 1-of-(n+1) selector.