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Details
Inventors: Behrens, Richard T.; Dudley, Trent; Bliss, William G.;
Assignee: Cirrus Logic, Inc. (Fremont, CA)
Primary Examiner: Psitos; Aristotelis M.
Assistant Examiner: Wamsley; Patrick
Attorney, Agent or Firm: Sheerin; Howard H., Shifrin; Dan A.

An improved timing recovery phase-locked loop in a partial response recording channel comprising a means for generating a frequency error and a means for generating a phase error represented by a timing gradient. The frequency error is not affected by a DC offset in the input reference signal and is less susciptible to noise due to an increase in sensitivity. A state machine for generating expected samples is used to generate the timing gradient, rather than estimated signal samples, which results in a shorter acquisition preamble. When tracking arbitrary user data, the timing gradient is smoothed to reduce variations in the gain of the loop.

DETAILED DESCRIPTION The objects of the present invention are achieved by utilizing an improved method and circuit for implementing timing recovery in a synchronous read channel.
A digital phase-locked loop (PLL), comprising a variable frequency oscillator (VFO), generates the sampling frequency of an analog-to-digital converter (A/D).
In order to lock the PLL to a nominal sampling frequency, a sinusoidal signal at one fourth the nominal sampling frequency is injected into the A/D.
A frequency error is computed utilizing three sample values which span more than half a period of the sinusoidal signal.
This method is unaffected by a DC offset and has an increase in signal-to-noise ratio due to an increase in sensitivity.
After locking the timing recovery loop to the nominal sampling frequency, a special training preamble is used to lock onto the actual sampling phase and frequency.
A timing gradient .
increment.
t, computed from the signal sample values and expected sample values corresponding to the known preamble, adjusts the sampling phase and frequency.
A state machine generates the expected sample values independent of the signal sample values, except to initialize the state machine to a starting state.
Thus, errors in reconstructing estimated sample values are avoided, which significantly reduces the length of the acquisition preamble.
This allows for faster, more efficient operation of the storage system.
A timing gradient adjuster circuit improves the reliability while tracking arbitrary user data by smoothing variations in the timing gradient .
increment.
t.
This is accomplished by increasing the timing gradient when one of the estimated sample values utilized in computing it is zero.
If all of the estimated sample values for computing the timing gradient are zero, then the timing gradient is copied from its prior value.
Smoothing the timing gradient reduces variations in gain which results in more effective timing recovery.
These and other features of the present invention will become apparent from the following detailed description of the preferred embodiments, which are disclosed in connection with the accompanying drawings



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