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System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
| Details |
Inventors: Chin, Kenneth T.; Coffee, Clarence K.; Collins, Michael J.; Johnson, Jerome J.; Jones, Phillip M.; Lester, Robert A.; Piccirillo, Gary J.;
Assignee: Compaq Computer Corporation (Houston, TX)
Primary Examiner: Shin; Christopher B.
Assistant Examiner:
Attorney, Agent or Firm: Daffer; Kevin L. Conley, Rose & Tayon
A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred across the processor bus consistent with the order in which the previous requests were transferred. |
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DETAILED DESCRIPTION The problems outlined above are in large part solved by an improved bus interface unit hereof.
The present bus interface unit can dispatch memory-destined request cycles (memory request cycles) concurrent with peripheral-destined request cycles (peripheral request cycles).
In this manner, peripheral request cycles can be immediately sent if the peripheral bus is clear or peripheral data is available.
Also important is the benefit of transferring a memory request cycle to system memory so that the processor optimally receives instructions or data stored therein.
The memory bus which receives memory requests or data from the bus interface unit is one which is compatible with high speed semiconductor memory.
Examples of suitable memory include: DRAM, synchronous DRAM (SDRAM).
A graphics-dedicated bus may also be coupled to the bus interface unit.
If the graphics bus is an AGP-PCI bus, then it may be linked to the bus interface unit by an AGP interface to effectuate (e.
g.
, 66 MHz 1.
times.
AGP transfers or 133 MHz 2.
times.
AGP data transfers).
The bus interface unit maintains a PCI interface which is synchronous to the processor interface and supports PCI burst cycles.
The graphics bus or mezzanine bus coupled to the bus interface unit may interchangeably be termed a "peripheral bus".
The term peripheral bus is generic in its application to any bus on which a peripheral device such as an electronic display, disk drive, printer, network interface card, SCSI, etc.
can be coupled.
Thus, a peripheral device generically involves an input/output device which is accessed within the input/output address space.
The present bus interface unit is configured as a north bridge between a processor local bus, a peripheral bus, and a memory bus.
The processor bus can link at least one, and certainly more, processors and associate cache storage locations within those processors.
Additionally, the memory bus links a memory controller within the bus interface unit to system memory denoted as semiconductor memory
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Processing Data 
