Test and control access architecture for an integrated circuit

DETAILED DESCRIPTION The present invention provides a microprocessor that has a bidirectional bus circuit, a central logic unit, and a plurality of peripheral logic units.
The bidirectional bus circuit includes a plurality of bus lines to couple the central logic unit to the peripheral logic units.
The bidirectional bus circuit also includes a plurality of bidirectional data repeaters.
Each data repeater has a plurality of data ports to couple to the bus lines.
One of the data ports is coupled to one peripheral logic unit.
The repeater further includes a peripheral cluster identification circuit to receive a peripheral identification signal from the central logic unit and to generate a directioning signal responsive to the peripheral identification signal.
The repeater also includes a directioning circuit to couple to the data ports and to the peripheral cluster identification circuit, and to receive data from one data port and to transmit the data to at least another data port in response to the directioning signal.