Tristatable output driver for use with 3.3 or 5 volt CMOS logic

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG.
1, PMOS (p-channel) and NMOS (n-channel) FETs 1 and 3 have their sources and drains connected in a series circuit between a supply rail VDD and ground.
The substrate of FET 1 is connected to the supply rail and the substrate of FET 3 is connected to ground.
The source and drain of a second PMOS FET 2 is connected in the above-described circuit, between FET 1 and the output terminal OUT.
The junction of FETs 1 and 2 is labeled as node N1.
The substrate of FET 2 is connected to the output terminal.
An NMOS FET 4 has its source or drain and its substrate connected to ground.
A PMOS FET 5 has its source or drain and its substrate connected to the output terminal.
The other of the sources or drains of FETs 4 and 5 are connected together and to the gate of FET 2, and form a node labeled N2.
An NMOS FET 6 has its respective drain and source terminals connected node N1 and ground, and its substrate connected to ground.
An NMOS FET 7 has its respective source and drain terminals connected to the voltage rail VDD and the output terminal, and its substrate connected to ground.
The gates of FETs 4 and 5 are connected together with the gate of FET 7 and are labeled HI.
The gate of FET 3 is labeled LO, the gate of FET 1 is labeled HIB, and the gate of FET 6 is labeled VREF.
A reference voltage is applied to VREF, and various logic levels are applied to HI, LO and HIB in accordance with the following truth table, wherein OUT represents the resulting logic level at the output terminal OUT:
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HI HIB LO OUT
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0 1 1 0
1 0 0 1
0 1 0 HIZ
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A "1" in the table above indicates a logic high (positive logic) and a "0" indicates a logic low for the given technology.
HIZ represents a high impedance state.
The leads HI, HIB and LO represent inputs to the circuit