Optical fiber connection monitoring apparatus, patch panel control system and method of using same
With an optical fiber patch panel in accordance with the invention, these problems associated with prior art optical fiber patch systems are eliminated. This is achieved by providing one optical patch... Read More
Inventors: Dietz, Jr., Frederick; Unger, Neil; Bateman, James;, Assignee: Data Switch Corporation (Shelton, CT) |
Software/hardware integration control system
In accordance with the illustrated embodiment, the disclosed integration control system (ICS) relieves the computer based instrument designer from having to design and debug hundreds to thousands of l... Read More
Inventors: JongeVos, Hendrik;, Assignee: Tektronix, Inc. (Beaverton, OR) |
Circuitry and method for performing branching without pipeline delay
It is therefore the object of the present invention to provide a method and system for minimizing delays caused by branch instructions in a pipeline computer architecture. The pipeline architecture of... Read More
Inventors: Underwood, Keith Frederick; Durante, Richard Joseph;, Assignee: Intel Corporation (Santa Clara, CA) |
Method and apparatus for networking data devices using an uplink module
In accordance with the present invention, the disadvantages and problems associated with collision detection in networks has been substantially reduced or eliminated. One aspect of the present inventi... Read More
Inventors: Scott, Craig M.; Wang, Li Tung; Bennett, Arthur T.; Nouri, Ahmad;, Assignee: Compaq Computer Corp. (Houston, TX) |
Flexible multi-frequency repeater
In accordance with the preferred embodiment of the present invention, a multi-segment repeater is set out. The multi-segment repeater includes a first inter-repeater bus and a second inter-repeater bu... Read More
Inventors: Melvin, Bruce W.;, Assignee: Hewlett-Packard Company (Palo Alto, CA) |
Synchronous stack bus for fast Ethernet repeater
To achieve the foregoing, the present invention provides a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the r... Read More
Inventors: Voloshin, Moshe; Cavaro, Mark D.;, Assignee: Cisco Technology, Inc (San Jose, CA) |
Method and system of managing virtualized physical memory in a data processing system
OF ILLUSTRATIVE EMBODIMENT(S) With reference now to the figures and in particular with reference to FIG. 1, there is illustrated a high-level block diagram of a multiprocessor (MP) data processing sy... Read More
Inventors: Arimilli, Ravi Kumar; Dodson, John Steven; Ghai, Sanjeev; Wright, Kenneth Lee;, Assignee: International Business Machines Corporation (Armonk, NY) |
High bandwidth PCI to packet switched router bridge having minimized memory latency
The present invention pertains to a mechanism in a computer system for minimizing memory latencies. An improved, high-speed packet switched router is used to route packets quickly and efficiently betw... Read More
Inventors: Miller, Steven C.;, Assignee: Silicon Graphics, Inc. (Mountain View, CA) |
PCI bus to IEEE 1394 bus translator
The present invention provides a PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The host computer includes an IEEE 1394 bus for coupling to remo... Read More
Inventors: Sescila, III, Glen O.; Odom, Brian K.; Schultz, Kevin L.;, Assignee: National Instruments Corporation (Austin, TX) |
Database system which adjusts the data storage order based on the processing speed of the storage media
This invention is intended to solve the above mentioned drawback of database systems. An object of the invention is to improve the throughput of the whole system through reduction of the average exclu... Read More
Inventors: Shiga, Shoji;, Assignee: NEC Corporation (Tokyo, JP) |
Exclusive control unit for a resource shared among computers
The invention has been made in order to solve the above-mentioned problems, and an object of the invention is to provide an exclusive control unit among computers which is able to reliably perform an ... Read More
Inventors: Sakakura, Takashi; Uemura, Jose;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Cache memory system
It is an object of the present invention to provide a system using virtual caches which is as fast as possible, while supporting the caches as efficiently as possible. The above identified objects of ... Read More
Inventors: Ramanujan, Raj K.; Steely, Jr., Simon C.; Bannon, Peter J.; Sager, David J.;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Alias address support
This invention is directed to certain hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating sy... Read More
Inventors: Loo, William V.; Watkins, John; Moran, Joseph; Shannon, William; Cheng, Ray;, Assignee: Sun Microsystems, Inc. (Mountain View, CA) |
Method and apparatus for servicing simultaneous I/O trap and debug traps in a microprocessor
Methods and apparatus for servicing a debug exception and I/O trap in a microprocessor that occur during execution of a single instruction are disclosed. In the following description, for purposes of... Read More
Inventors: Thangadurai, George; Chung, Chih-Hung;, Assignee: Intel Corporation (Santa Clara, CA) |
Flexible implementation of a system management mode (SMM) in a processor
In accordance with the present invention, a system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most o... Read More
Inventors: Favor, John G.; Weber, Frederick D.;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Method and apparatus for creating formatted fat partitions with a hard drive having a BIOS-less controller
Broadly speaking, the present invention fills these needs by providing a method and apparatus for creating and formatting FAT partitions beyond the first gigabyte of a disk having more than one gigaby... Read More
Inventors: Lin, Yen-Chung; Bui, Thanh Tu;, Assignee: Adaptec, Inc. (Milpitas, CA) |
Apparatus and method for TLB purge reduction in a multi-level machine system
The present invention is directed to improving the performance of the translation lookaside buffer (TLB) by reducing the purging of the entire TLB through a more effective analysis of the requirement ... Read More
Inventors: Gannon, Patrick M.; Gum, Peter H.; Hough, Roger E.; Murray, Robert E.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Method and system for remapping memory from one physical configuration to another physical configuration
OF A PREFERRED EMBODIMENT OF THE INVENTION Referring now to FIG. 1 of the drawings, in this simplified illustrative embodiment of the invention, a MEMORY system 10, which initially has two active mod... Read More
Inventors: Salsburg, Linda B.;, Assignee: Unisys Corporation (Blue Bell, PA) |
Method and apparatus for decoding and recoding of addresses
A novel semiconductor component is described which directs transmission of data. The component comprises of a decoder device coupled to said first memory device capable of decoding an address of said ... Read More
Inventors: Lent, David D.; Dunn, Daniel J.;, Assignee: Intel Corporation (Santa Clara, CA) |
Apparatus and method for address translation in bus bridge devices
The present invention relates to apparatus and methods for handling incompatibility issues between elements of a computer architecture. In particular, the invention relates to handling information tra... Read More
Inventors: Jander, Mark J.; Solomon, Richard L.;, Assignee: LSI Logic Corporation (Milpitas, CA) |
Method and apparatus for intelligent configuration register access on a PCI to PCI bridge
In accordance with the present invention, a method and apparatus for intelligent configuration register access on a PCI to PCI bridge are provided that substantially eliminate or reduce problems assoc... Read More
Inventors: Rekeita, David W.; Patel, Krunali; Dickens, David E.;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Method and apparatus for interrupt signaling in a computer system
From the foregoing, it can be appreciated that a computer system's architecture may be enhanced in a manner that provides flexibility and reduces the cost of implementing peripherals, as well as reduc... Read More
Inventors: Kardach, James; Cho, Sung S.; Peterson, Nicholas B.; Lane, Thomas R.;, Assignee: Intel Corporation (Santa Clara, CA) |
Data processor and data processing system
With the conventional technique outlined above, the debug command functions are predetermined fixedly and are thus limitative of the degree of flexibility with which to set simulated internal states f... Read More
Inventors: Hasegawa, Hironobu; Sasaki, Hiroyuki; Uraguchi, Masahiko;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Multi-delivery scheme interrupt router
Referring to FIG. 1, a computer system implementing a traditional interrupt routing scheme according to an embodiment of the present invention is shown. The computer system 100 comprises a processor ... Read More
Inventors: Tetrick, Raymond S.;, Assignee: Intel Corporation (Santa Clara, CA) |
Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network node
Accordingly, there is provided a status report frequency mitigation method and corresponding apparatus for mitigating the frequency of status report generation of raw cells during transmit operations ... Read More
Inventors: Ross, Theodore L.; Washabaugh, Douglas M.; Roman, Peter J.; Cheung, Wing; Tanaka, Koichi; Mizuguchi, Shinichi; Thomas, Robert E.;, Assignee: Enterasys Networks, Inc. (Portsmouth, NH) |
Logic control system including cache memory for CPU-memory transfers
What is claimed is: 1. A hardware/firmware logic control system in a data processing system including a central memory system and a central processing unit (CPU) with a firmware control system in elec... Read More
Inventors: Lemay, Richard A.; Stanley, Philip E.; Woods, William E.; Cushing, David E.;, Assignee: Honeywell Information Systems Inc. (Waltham, MA) |
Apparatus and method for supporting a transfer trapping discipline for a non-enabled peripheral unit within a computing system
The present invention is an apparatus for managing communication within a computing system which selectively employs a transfer trapping discipline. The computing system includes a processing unit and... Read More
Inventors: Gephardt, Douglas D.; McBride, Andrew;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Central monitoring and alarming system
The present invention is to solve the above-mentioned problems. An object of the present invention is to provide a central monitoring and alarming system in which an operator can know an address assig... Read More
Inventors: Kimura, Tetsuo;, Assignee: Nittan Company Ltd. (JP) |
Method and apparatus for coordinating data transfer between hardware and software by comparing entry number of data to be transferred data to entry number of transferred data
A method and apparatus of coordinating data transfer between hardware and software in a computer system through the use of a semaphore mechanism is disclosed. When a data packet is queued by preparing... Read More
Inventors: Oskouy, Rasoul M.; Gentry, Denton E.;, Assignee: Sun Microsystems, Inc. (Mountain View, CA) |
System for creating new group of chain descriptors by updating link value of last descriptor of group and rereading link value of the updating descriptor
In accordance with one aspect of the invention, an improved method and apparatus for appending chain descriptors for use by a DMA unit of a computer system is provided. To append chain descriptors, a ... Read More
Inventors: Gillespie, Byron; Garbus, Elliot; Futral, William;, Assignee: Intel Corporation (Santa Clara, CA) |
Processing Data 
