Advanced titanium silicide process for very narrow polysilicon lines

DETAILED DESCRIPTION It is an object of this invention to form a low resistance, titanium silicide layer, for use as a component for narrow, less than 0.
20 micrometer width, polycide word lines.
It is another object of this invention to perform a pre-amorphization, ion implantation procedure, prior to titanium deposition.
It is still another object of this invention to perform an ion mixing procedure, via ion implantation into the titanium layer, prior to the anneal procedure, used to form titanium silicide.
In accordance with the present invention, a process is described for forming a low resistance, titanium silicide layer, for a narrow width, polycide gate structure, via a combination of pre-titanium, and post-titanium, ion implantation procedures.
After creation of: a narrow width, polysilicon line; a lightly doped source/drain region; insulator spacers on the sides of the narrow width, polysilicon line; and a heavily doped source/drain region; a pre-amorphization, ion implantation procedure is performed, to exposed polysilicon and silicon regions, using germanium or arsenic ions.
After deposition of a titanium, or titanium nitride layer, an ion mixing, ion implantation procedure is used to place germanium or silicon ions, in the titanium, or titanium nitride--titanium layer, near the metal--silicon interface.
A first anneal procedure, converts titanium , overlying silicon or polysilicon, to a first phase titanium silicide layer, while titanium overlying insulator layers, remain unreacted.
After selective removal of the unreacted titanium, a second anneal is used to convert the first titanium silicide phase, to a more conductive second titanium silicide phase, resulting in a narrow width, polycide gate structure, featuring low word line resistance as a result of forming the low resistance, titanium silicide layer, using the combination of ion implantation procedures, described above.