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Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer
| Details |
Inventors: Kadosh, Daniel; Hause, Fred N.; Cheek, Jon D.;
Assignee: Advanced Micro Devices, Inc. ()
Primary Examiner: Chaudhari; Chandra
Assistant Examiner:
Attorney, Agent or Firm: Daffer; Kevin L. Conley, Rose & Tayon
Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits. |
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DETAILED DESCRIPTION The problems outlined above are in large part solved by an improved transistor configuration.
The transistor can be either a p-channel or n-channel transistor.
The transistor hereof is classified as an asymmetrical transistor, wherein the drain-side LDD implant adjacent the channel is purposefully made larger in lateral area than the source-side LDD implant.
There are various mechanisms used henceforth to achieve the asymmetrical configuration either on a p-channel or n-channel transistor.
Regardless of the processing steps used, the result is a transistor having an LDD implant primarily or exclusively in only the critical region defined as the junction between the drain and the channel.
Proper LDD design is achieved by incorporating a relatively large lateral area LDD implant at the drain-side of the channel while minimizing if not eliminating LDD implant at the source-side of the channel.
LDD implant focused primarily at the drain side maintains parasitic resistance of the drain LDD (i.
e.
, R.
sub.
D) but reduces if not eliminates parasitic resistance R.
sub.
S associated with the source-side LDD implant.
Thus, the drain-engineered structure hereof serves to attenuate the maximum electric field Em in the critical drain area while reducing parasitic resistance R.
sub.
S in the source area.
The drain-side LDD region is bounded by a junction which exists below the gate edge and far below the silicon surface.
The LDD area, however, is attributed solely or primarily to the critical area near the drain.
Shifting of the electric field, Em, occurs only in the region where shifting is necessary, i.
e.
, only in the drain-side of the channel.
The p- or n-channel transistor formed as a result of the present LDD design receives the benefit of reduced HCI but not at the expense of performance (i.
e.
, switching speed or saturation current).
Even when Leff is less than 2.
0 .
mu.
m, where SCE would normally be a problem, the present LDD-embodied transistors experiences minimal sub-threshold currents
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