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| Silicon layer having increased surface area and method for manufacturing |
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| Process for forming a thin oxide layer |
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Compact, real time tape drive system
| Details |
Inventors: Cogley, Jr., John R.;
Assignee: Qualstar Corporation (Chatsworth, CA)
Primary Examiner: Smith; Jerry
Assistant Examiner: Baker; Stephen M.
Attorney, Agent or Firm: Poms, Smith, Lande & Rose
A nine track digital tape system operating in accordance with a feedback shift register redundancy scheme, includes in both the encoding and writing section and in the reading and error correction section, arrangements for shifting successive bytes of information by one digit place, and adding the shifted bytes, to provide a "low product" and a "high product", constituting an address or "pointer" to a modifier table, from which a modifier value is obtained to be added to the "low product". In the error correction circuitry, additional tables, using a sample parity error vector and an identification of the columns in which errors occur, as "pointers", provide data which is used to calculate error correction vectors. Instead of using feedback registers, and complex decoding hardware, the circuitry obtains the same result as would have been obtained by the hardware, in a unique manner, to provide a simple, high speed, error correction system. |
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DETAILED DESCRIPTION In accordance with the present invention, the foregoing objectives are achieved by a microprocessor implementation of the encoding and decoding functions, as outlined hereinabove, and employing simplified algorithms which are convenient for a microprocessor to implement, together with "Look-Up" tables stored in Read Only Memories, to accomplish the encoding and decoding functions.
More specifically, concerning the encoding arrangements, the parity bit for each eight bit byte is calculated in a normal manner and added to each eight bit byte to form the 9-bit "bytes".
Concerning the development of the eight bit error correction byte, a product is formed by offsetting the successive information bytes of the basic data block by one bit, and adding the resultant columns, modulo 2.
The result is a product which can be separated into an eight bit "low" portion of the product and a seven bit "high" portion of the product.
Recognizing that the seven bits of the high portion of the product can only have 128 values (two raised to the seventh power), reference is now made to a table, designated the M Table (M for "Modifier"), using the high portion of the product as the address, and the resultant number from the table is added to the low portion of the product to give the error correction code or ECC byte.
In this regard, the inventor has determined that the same value from the look-up table will always give the correct ECC byte, when it is added to the low portion of the product.
This is a result of the cyclic nature of the output from the feedback shift register by which the error correction code was originally formed.
The 9.
times.
8 bit array is then completed by determining the parity check bit for the 8-bit ECC byte.
Now, turning to the reading section, consideration will be given to the detection and correction of errors.
Initial, relatively simple steps involve separately checking each byte of 9 bits for parity, and obtaining an eight bit parity vector.
Of course, if there are no errors in the block of data, the parity check vector will be all zeros
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