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 Method of fabricating a high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory
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 Methods for forming a control gate apparatus in non-volatile memory semiconductor devices
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 Method for fabricating a capacitor
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 4-Aminothiazole
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 Dielectric barrier material

Details
Inventors: Erie, David G.; Roberts, Jon A.; Lee, Eddie C.;
Assignee: Honeywell Inc. (Minneapolis, MN)
Primary Examiner: Powell; William A.
Assistant Examiner:
Attorney, Agent or Firm: Udseth; William T.

Disclosed is a method of fabricating an integrated circuit. A substrate comprising a semiconductor material and having a first surface is provided. A first layer of metalization interconnects is formed on the first surface. A first thin film layer comprising a dielectric barrier material is deposited over the first layer of metalization interconnects. A second thin film layer comprising a dielectric passivating material is deposited over the first thin film layer of dielectric barrier material. A via having a width greater than the width of a metalization interconnect is then plasma etched in the dielectric passivating material using a first etch gas. The dielectric barrier material is then plasma etched using a second etch gas to remove the dielectric barrier material in the area of the via. A second layer of metalization interconnects is then formed, a metalization interconnect in each of the first and second layers of metalization interconnects being connected in the via.

DETAILED DESCRIPTION The present invention comprises a method of fabricating an integrated circuit.
A substrate comprising a semiconductor material and having a first surface is provided.
A first layer of metalization interconnects is formed on the first surface.
A first thin film layer comprising a dielectric barrier material is deposited over the first layer of metalization interconnects.
A second thin film layer comprising a dielectric passivating material is deposited over the first thin film layer of dielectric barrier material.
A via having a width greater than the width of a metalization interconnect is then plasma etched in the dielectric passivating material using a first etch gas.
The dielectric barrier material is then plasma etched using a second etch gas to remove the dielectric barrier material in the area of the via.
A second layer of metalization interconnect in each of the first and second layers of metalization interconnects being connected in the via.



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