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Formation of air gap structures for inter-metal dielectric application
| Details |
Inventors: Soo, Choi Pheng; Tee, Kheng Chok; Ong, Kok Keng; Chan, Lap;
Assignee: Chartered Semiconductor Manufacturing Company (Singapore, SG); National University of Singapore (Singapore, SG); Nanyang Technological University of Singapore (Singapore, SG)
Primary Examiner: Picardat; Kevin M.
Assistant Examiner: Collins; D. M.
Attorney, Agent or Firm: Saile; George O., Pike; Rosemary L.S.
A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS. |
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DETAILED DESCRIPTION The principal object of the present invention is to provide an effective and manufacturable method of forming air gaps between conductive layers of material.
Another objective of the present invention is a method of reducing the dielectric constant k between conductive layers of material.
Another objective of the present invention is a method of reducing capacitive coupling between conducting layers of material.
Another objective of the present invention is a method of reducing capacitive crosstalk between conductive layers of material.
Another objective of the present invention is to reduce the potential for false or incorrect logic levels of the circuits in the IC's.
Another objective of the present invention is a method of reducing Resistive Capacitive delays of the circuits in the IC's.
Another objective of the present invention is to increase Switching Speed of the circuits in the IC's.
In accordance with the objects of the present invention a new method of forming air gaps between adjacent conducting lines of a semiconductor circuit is achieved.
A metal pattern of metal lines is in the standard manner deposited on a semiconductor substrate.
A layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern using Plasma Enhanced Chemical Vapor Deposition (PECVD).
Chemical Mechanical Polarization (CMP) is performed to achieve planarity of the deposited PPMS resist.
This step is optional.
A reticle is interposed between a source of radiation and the surface of the created PPMS resist.
The surface of the PPMS resist is subjected to deep ultraviolet (UV) exposure (with radiation wavelength of 193 nm.
, 248 nm.
, etc.
) or by E-beam radiation.
The exposure depth is controlled during this exposure.
The surface of the PPMS resists is selectively (via the reticle) exposed, the PPMS is bleached or exposed down to slightly below the top of the metal lines, the PPMS is in this manner converted to PPMSO.
Columns of unexposed PPMS are created in the areas that are protected or shielded by the reticle
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Quantum Computing 
