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High voltage semiconductor device capable of increasing a switching speed
| Details |
Inventors: Nakagawa, Akio; Matsudai, Tomoko;
Assignee: Kabushiki Kaisha Toshiba (Tokyo, JP)
Primary Examiner: Loke; Steven
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
An IGBT has a punch-through structure including an n.sup.+ buffer layer. It includes a p.sup.- low concentration layer formed between the n.sup.+ buffer layer and a p.sup.+ drain layer. Owing to the low concentration layer, the drain current decreases to zero gradually, not rapidly, when the IGBT is turned off. |
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DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will now be described with reference to the accompanying drawings.
(First Embodiment) FIG.
1 is a cross-sectional view showing a structure of an IGBT according to a first embodiment of the present invention.
The IGBT has the punch-through structure including an n.
sup.
+ buffer layer 13.
It is characterized in that a p.
sup.
- (or n.
sup.
-) low concentration layer 12 is interposed between the buffer layer 13 and an p.
sup.
+ drain layer 11.
More specifically, in the IGBT 10, for example, the p.
sup.
- low concentration layer 12 is formed on the p.
sup.
+ drain layer 11.
The n.
sup.
+ buffer layer 13 is formed on the low concentration layer 12.
An n.
sup.
- epitaxial layer 14 is formed on the buffer layer 13.
A p type base layer 15 is formed on the epitaxial layer 14.
An n.
sup.
+ source region 16 is formed in a surface region of the base layer 15.
A gate electrode 17 of the trench structure is formed in the source region 16, the base layer 15 and the epitaxial layer 14.
The gate electrode 17 is insulated by a gate insulating film 18 from the source region 16, the base layer 15 and the epitaxial layer 14.
A source electrode 19 made of, for example, aluminum, is formed on the overall surfaces of the base layer 15 and the source region 16.
A drain electrode 20 is formed on the drain layer 11.
FIG.
2 shows the relationship between the thickness and the imparity concentration of each of the layers of the IGBT shown in FIG.
1.
As shown in FIG.
2, the buffer layer 13 has a thickness of, for example, 5 .
mu.
m and an impurity concentration of, for example, 1.
times.
10.
sup.
17 cm.
sup.
-3.
The drain layer 11 has a thickness of, for example, 0.
3 .
mu.
m and an impurity concentration of, for example, 2.
times.
10.
sup.
18 cm.
sup.
-3.
The low concentration layer 12 has a thickness of, for example, 0.
5 .
mu.
m to 30 .
mu.
m and an impurity concentration of, for example, 1.
times.
10.
sup.
16 cm.
sup.
-3.
The buffer layer 13 has the aforementioned thickness in a case where the impurity is arsenic
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Quantum Computing 
