Logic circuit using vertically stacked heterojunction field effect transistors

DETAILED DESCRIPTION The advantages of the present invention are achieved by a heterojunction field effect transistor structure having vertically stacked complementary devices.
A P-channel quantum well and an N-channel quantum well are formed near each other under a single gate electrode and separated from each other by a thin layer of barrier material.
P-source and P-drain regions couple to the P-channel.
N-source and N-drain regions couple to the N-channel.
The P-source/drain regions are electrically isolated from the N-source/drain regions so that the P-channel and N-channel devices may be interconnected to provide many logic functions.