 Electrically erasable programmable logic device |
| The preferred embodiment in accordance with the present invention will be discussed in detail with ... |
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| Short channel IGBT with improved forward voltage drop and improved switching power loss |
| OF THE DRAWINGS Referring first to FIGS. 1 and 2, there is shown a portion of the active area of a ... |
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| Semiconductor non-volatile memory device having a NAND cell structure |
| In light of the above, therefore, it is an object of the invention to provide an improved non-... |
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| Light-emitting diode matrix with semi-insulating zones |
| What is claimed is: 1. A matrix of light-emitting diodes connected by conducting contacts and ... |
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| Solid state light source for emitting light over a broad spectral band |
| According to the invention, there is provided a solid state light source for generating light in ... |
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| Detecting lateral position of webs |
| I claim: 1. Apparatus for measuring the lateral position of a web as the web is fed along a ... |
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| Web guide apparatus |
| OF THE PREFERRED EMBODIMENT Referring to FIG. 1 there is shown a diagrammatic illustration of a ... |
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| Storage stable paper size composition containing ethoxylated lanolin |
| OF THE PREFERRED EMBODIMENTS The sizing compounds contemplated for use herein are the cyclic ... |
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| Nanoscale modulation doping method |
| In accordance with the present invention, a nanoscale modulation doping method combines a focused ... |
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MOSFET with a high permitivity gate dielectric
| Details |
Inventors: Wu, Shye-Lin;
Assignee: Texas Instruments--Acer Incorporated (Hsinchu, TW)
Primary Examiner: Chaudhuri; Olik
Assistant Examiner: Bentley; Dwayne L.
Attorney, Agent or Firm: Merchant, Gould, Smith, Edell, Welter & Schmidt
A transistor formed on a semi-conductor substrate, where the transistor includes a gate dielectric layer formed on the semi-conductor substrate. The gate dielectric layer includes a silicon oxynitride sub-layer formed on the semi-conductor substrate and a dielectric sub-layer having relatively high permitivity to an oxide formed on the silicon oxynitride sub-layer. The transistor also includes a barrier layer formed on the gate dielectric layer and a metal gate is formed on the barrier layer. The gate dielectric layer, the barrier layer and the metal gate combine to form a gate structure. Side walls spacers are formed on side walls of the gate structure, and extended source, drain junctions are formed under the side wall spacers in the semi-conductor substrate and adjacent to the gate structure. The transistor also includes source and drain junctions formed in the gate structure next to the extended source, drain junctions. |
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DETAILED DESCRIPTION The method of the present invention includes forming a silicon oxynitride layer on a substrate.
The silicon oxynitride layer is preferably deposited by thermal oxidation in N.
sub.
2 O or NO ambient.
Then, a dielectric layer with high permitivity is deposited by chemical vapor deposition on the silicon oxynitride layer.
The dielectric layer is chosen from a group of TiO.
sub.
2, Ta.
sub.
2 O.
sub.
5, PZT or BST.
Subsequently, a rapid thermal process (RTP) anneal is performed at a temperature about 800 to 900 centigrade in N.
sub.
2 O or NO ambient to reduce the dielectric leakage.
A multiple conductive layer is then formed on the dielectric layer.
The multiple conductive layer is consisted of a TiN layer that is formed on the dielectric layer to serve as a barrier metal layer.
A metal layer is formed on the TiN layer for acting a gate of a transistor.
Preferably, the metal layer is formed of titanium or tungsten.
Next, an anti-refractive coating (ARC) layer is formed on the metal layer.
Then, the multiple conductive layer, the dielectric layer, and the silicon oxynitride layer are patterned to form gate structure.
A plasma immersion is performed to form ultra shallow extended source and drain junctions adjacent to the gate structure.
Side wall spacers are formed on the side walls of the gate structure.
Next, an ion implantation is carried out to dope ions into the substrate.
Next, a rapid thermal process (RTP) anneal is performed to form shallow junctions of the source and the drain.
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Quantum Computing 
