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Method for fabricating VDMOS transistor with improved breakdown characteristics
| Details |
Inventors: Contiero, Claudio; Galbiati, Paola; Zullino, Lucia;
Assignee: SGS-Thomson Microelectronics, S.r.l. (Agrate Brianza, IT)
Primary Examiner: Fourson; George
Assistant Examiner: Pham; Long
Attorney, Agent or Firm: Groover; Robert, Formby; Betty, Anderson; Matthew
The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor. |
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DETAILED DESCRIPTION What is claimed is: 1.
A method for fabricating vertical-current-flow field-effect transistors, comprising the steps of: (a.
) providing a substrate which includes at least one substantially monolithic volume of semiconductor material having a first conductivity type in proximity to a first surface thereof, and having a buried layer of a high concentration of said first conductivity type therebelow; (b.
) implanting said first surface with dopants having a second conductivity type, to form body regions in locations; (c.
) forming thick insulator regions to cover substantially all of said surface except for active area locations; (d.
) implanting said first surface with dopants of said first conductivity type, to form source regions within said body regions; (e.
) forming insulated gate regions on said first surface which are each capacitively coupled to at least some portion of said body region at said first surface; (f.
) forming ohmic contacts to said source regions; and (g.
) forming ohmic contacts to said buried layer; wherein ones of said source, gate, and body regions are formed to define at least one matrix comprising a plurality of cells, each cell comprising at least a portion of one of said source regions and a portion of one of said body regions, said matrix being laterally surrounded by a portion of said thick insulator region which is underlain by a field-isolation diffusion which is electrically connected to said body region of at least some ones of said cells of said matrix, and which is overlain by a field plate which is electrically connected to said gate region.
2.
The method of claim 1, wherein said semiconductor material consists essentially of silicon.
3.
The method of claim 1, wherein said first conductivity type is N-type.
4.
The method of claim 1, wherein said monolithic volume is an epitaxial layer formed over a monocrystalline substrate, and said substrate is doped with said first conductivity type, at a higher dopant concentration than said epitaxial layer
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Quantum Computing 
