Method for formation of a stacked capacitor

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following disclosure of the invention is submitted in furtherance with the constitutional purpose of the Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8).
In accordance with one aspect of the invention, a method of forming a capacitor on a semiconductor wafer comprises the following steps: forming an electrically conductive interconnect line on the wafer, the interconnect line having side and top portions; electrically isolating the substantial side and top portions of the interconnect line by forming one or more electrically insulating layers about the side and top portions; forming a first dielectric layer over the wafer atop the substantially insulated interconnect line, the first dielectric layer having a first etch rate; forming a second dielectric layer over the wafer atop the first dielectric layer, the second dielectric layer having a second etch rate which is slower than the first etch rate; selectively etching contact openings through the first and second dielectric layers to align with selective active areas on the wafer; applying an electrically conductive material atop the wafer, the electrically conductive material engaging the active areas within the contact openings; selectively etching the applied electrically conductive material and the second dielectric layer down to the first dielectric layer to begin formation of a first terminal of a capacitor, the first capacitor terminal rising above and over the interconnect line; forming an oxide layer atop the electrically conductive material to enable texturizing of a top of the first capacitor terminal to increase capacitance, the oxide layer having an etch rate which is slower than the first etch rate; etching the first dielectric layer to project the first capacitor terminal above the interconnect line to expose a bottom as well as top and side portions of the first capacitor terminal above the interconnect line; etching the oxide layer and remaining second dielectric layer from the projecting first capacitor terminal; forming a third dielectric layer over the exposed top, bottom and side portions of the exposed and etched projecting first capacitor terminal; and applying an electrically conductive material atop the third dielectric layer to form a second terminal of the capacitor