Home | Links | Contact Us | More About Intellectual Property | Bookmark

Search patents:

Home

Quantum Computing

Method-for-manufacturing-semiconductor-device

PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OF OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT

The invention comprises a process for inhibiting the passage of dopant from a thin polysilicon gate ...

Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device

An object of the invention is to provide a process for forming a layer of polycrystalline silicon ...

Method for suppressing boron penetration in PMOS with nitridized polysilicon gate

OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a preferred embodiment according to the present ...

Selective diffusion process for forming both n-type and p-type gates with a single masking step

In accordance with this invention, both first and second conductivity type regions are formed in a ...

Nitrogenated gate structure for improved transistor performance and method for making same

The problems outlined above are in large part addressed by a method of fabricating an integrated ...

Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer

The problems outlined above are in large part solved by an improved transistor configuration. The ...

Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device

These needs and others are met by the present invention, which in accordance with certain aspects, ...

Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening

The present invention provides a method for hardening of gate oxide without forming low boron ...

Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control

The present invention is directed to a SOI MOSFET device that includes a dynamic threshold voltage ...

Heating method of semiconductor wafer

With the foregoing in view, the present invention has as its object the provision of a heating ...

Method for manufacturing semiconductor device

Details

Inventors: Yoshida, Kazuhiro;
Assignee: Murata Manufacturing Co., Ltd. (JP)
Primary Examiner: Nguyen; Tuan H.
Assistant Examiner:
Attorney, Agent or Firm: Ostrolenk, Faber, Gerb & Soffen, LLP

A semiconductor device manufacturing method with which a GaAs MESFET and an integrated circuit using the same can be manufactured cheaply and with high yield by accurately forming a mushroom-shaped gate electrode with inexpensive equipment and a short process. The method includes the steps of: depositing a first mask layer on a semiconductor substrate; forming an opening in the first mask layer; causing the first mask layer to flow by heat-treating the semiconductor substrate; depositing a second mask layer on the first mask layer; forming in the second mask layer an opening larger than the opening in the first mask layer and exposing the opening in the first mask layer; and forming a gate electrode in the opening in the second mask layer.

DETAILED DESCRIPTION It is an object of the present invention to provide a method for manufacturing a semiconductor device which solves the above-mentioned problems and with which a GaAs MESFET and an integrated circuit using the same can be manufactured cheaply and with high yield by accurately forming a mushroom-shaped gate electrode with inexpensive equipment and a less complicated process.
To solve the above-mentioned problems, the invention provides a method for manufacturing a semiconductor device.
The method includes the steps of: depositing a first mask layer on a semiconductor substrate; forming an opening in the first mask layer; causing the first mask layer to flow by heat-treating the semiconductor substrate; depositing a second mask layer on the first mask layer; forming an opening in the second mask layer larger than the opening in the first mask layer and exposing the opening in the first mask layer; and depositing metal constituting a gate electrode in the opening in the second mask layer.
In a semiconductor device manufacturing method according to the invention, because no step of forming an opening in an insulating film by etching is employed, the gate length is determined only by the width of the opening in a resist layer constituting the first mask layer.
As a result, it is possible to form the opening in the resist layer with good control of the width of the opening without damaging the surface of an active layer directly below the gate electrode.
Also, because there is no step of forming an opening in an insulating film and no step of removing the resist film constituting the first mask layer, the process can be simplified.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

Related patents

	Planar interconnect for integrated circuits It is an object of the subject invention to provide an integrated circuit having a dense multilayer metallization. More specifically, it is an object of this invention ...
	Logic circuit using vertically stacked heterojunction field effect transistors The advantages of the present invention are achieved by a heterojunction field effect transistor structure having vertically stacked complementary devices. A P-channel ...
	Method of making substantially linear field-effect transistor The device and the method of making the same discussed in this application has substantial commonality with the devices, and method of making those devices, as ...
	Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts Briefly stated, the scope of the present invention encompasses a III-V complementary semiconductor device employing compatible ohmic contacts. Specifically, a preferred ...
	SiC/111-V-nitride heterostructures on SiC/SiO.sub.2 /Si for optoelectronic devices These problems and needs will be met in accordance with a preferred embodiment of the invention by converting 100% of a 100-500 .ANG. layer of Si of a silicon-on-...
	Separation of thin films from transparent substrates by selective optical processing The invention may be summarized as a method of transferring a crystalline film from a growth substrate to an acceptor substrate. The film of one composition is grown on ...
	Apparatus comprising refractive means for elections OF SOME EXEMPLARY EMBODIMENTS Before describing some currently preferred embodiments we will derive expressions describing the effect of a potential step on the ...
	Nonvolatile ferroelectric memory and a method of manufacturing the same Therefore, the present invention is directed to solve the problems of the conventional FRAM and is to provide a nonvolatile ferroelectric memory device having SWL ...
	Filamentary electron-emission device having self-aligned gate or/and lower conductive/resistive region What is claimed is: 1. A structure comprising: a substrate for providing structural support; a lower electrically conductive region comprising a group of generally ...
	Methods of forming materials within openings, and method of forming isolation regions In one aspect, the invention encompasses a method of forming a material within an opening. An etch-stop layer is formed over a substrate. The etch-stop layer has an ...

0.044
Archive: All patents - Links Copyright (c)2006 Eipa-patents.org - All rights reserved