Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device

DETAILED DESCRIPTION It is an object of this invention to create a DRAM device, comprised of a stacked capacitor, (STC), structure, and metal contact structures.
It is another object of this invention to use a single process sequence to simultaneously form both the capacitor plate, of the STC structure, and a metal contact structure.
It is still another object of this invention to simultaneously form a capacitor plate, comprised of a tungsten layer, overlying a titanium nitride barrier layer, while forming a tungsten - titanium nitride, metal contact structure, with the metal contact structure overlying a region of the semiconductor substrate, exposed in a via hole.
In accordance with the present invention a process is described, for fabricating a high density DRAM device, in which the capacitor plate, of an STC structure, and a metal contact structure, are formed simultaneously, using the same materials, and using the same process sequence.
Polycide gate structures, comprised of tungsten silicide on polysilicon, encapsulated by an overlying silicon nitride layer, and silicon nitride sidewall spacers, are formed on a thin gate insulator layer.
After formation of source and drain regions, in the semiconductor substrate, between polycide gate structures, polysilicon contact plugs are formed in contact holes, in a first insulator layer, with the polysilicon contact plugs, contacting the top surface of source and drain regions.
Polycide bit line structures, comprised of tungsten silicide on polysilicon, are formed in via holes, in a second insulator layer, contacting the underlying polysilicon pads that are used for bit line contact to the source and drain regions of the semiconductor substrate.
A storage node contact hole, is opened in a third insulator layer, and in the second insulator layer, exposing the top surface of a polysilicon contact pad, that is used for capacitor contact to a source and drain region of the semiconductor substrate.
A polysilicon storage node structure, with an overlying capacitor dielectric layer, is next formed in the storage node contact hole, followed by the opening of a first contact hole, in the third insulator layer, in the second insulator layer, and in the first insulator layer, exposing a source and drain region of the semiconductor substrate