Home | Links | Contact Us | More About Intellectual Property | Bookmark

Search patents:

Home

Quantum Computing

Method-of-depositing-thin-nitride-layer-on-gate-oxide-dielectric

Short channel IGBT with improved forward voltage drop and improved switching power loss

OF THE DRAWINGS Referring first to FIGS. 1 and 2, there is shown a portion of the active area of a ...

Semiconductor non-volatile memory device having a NAND cell structure

In light of the above, therefore, it is an object of the invention to provide an improved non-...

Light-emitting diode matrix with semi-insulating zones

What is claimed is: 1. A matrix of light-emitting diodes connected by conducting contacts and ...

Solid state light source for emitting light over a broad spectral band

According to the invention, there is provided a solid state light source for generating light in ...

Detecting lateral position of webs

I claim: 1. Apparatus for measuring the lateral position of a web as the web is fed along a ...

Web guide apparatus

OF THE PREFERRED EMBODIMENT Referring to FIG. 1 there is shown a diagrammatic illustration of a ...

Storage stable paper size composition containing ethoxylated lanolin

OF THE PREFERRED EMBODIMENTS The sizing compounds contemplated for use herein are the cyclic ...

Nanoscale modulation doping method

In accordance with the present invention, a nanoscale modulation doping method combines a focused ...

Creatine kinase isoenzyme electrophoretic technique and improved creatine kinase isoenzyme reagent for use therein

The embodiments of the invention in which an exclusive property or privilege is claimed are defined ...

Gold recovery system

The invention is a process for recovering gold from dilute aqueous solution using an electrolytic ...

Method of depositing thin nitride layer on gate oxide dielectric

Details

Inventors: Bryant, Frank Randolph;
Assignee: SGS-Thomson Microelectronics, Inc. (Carrollton, TX)
Primary Examiner: Niebling; John
Assistant Examiner: Booth; Richard A.
Attorney, Agent or Firm: Galanthay; Theodore E., Hill; Kenneth C., Jorgenson; Lisa K.

A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

DETAILED DESCRIPTION The present invention is a gate structure in a transistor and method for fabricating the structure.
A gate structure is formed on a substrate.
The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer.
The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer.
The gate structure is reoxidized to form a layer of oxide over the gate structure.
The nitride layer prevents the formation of asperities on the underside of the polysilicon layer during reoxidation of the transistor.

Related patents

	Method of forming high density flash memories with MIM structure The method of the present invention includes forming a gate oxide layer on a substrate. Subsequently, a doped polysilicon layer is deposited on the gate oxide layer. T...
	Method for fabricating a capacitor The invention provides a method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. ...
	4-Aminothiazole What is claimed is: 1. 4-Aminothiazole and its acid addition salts. 2. The compound of claim 1 being the base of the structure: ##SPC1## 3. The compound of claim 1 being ...
	Single poly memory cell and array In light of the above, it is an object of the invention to provide an improved non-volatile semiconductor memory device that provides the lowest possible cost compared ...
	Etox cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current An ETOX cell formed in a semiconductor substrate is disclosed. The ETOX cell comprises: a p-well formed within said substrate; a floating-gate formed above said p-well, ...
	Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device Our preceding patent application has proposed the use of storage elements of one flash memory for repairing a defect or to effect trimming within a closed range of the ...
	Semiconductor device having sidewall insulating film It is therefore an object of the present invention to prevent effectively the formation of fence-shaped residue when a conductive layer formed on a sidewall insulating ...
	Method of making split gate flash EEPROM cell by separating the tunneling region from the channel What is claimed is: 1. A method manufacturing a flash EEPROM cell, comprising the steps of: forming a buried drain region in a portion of a silicon substrate; forming a ...
	Semiconductor memory device having word line conductors provided at lower level than memory cell capacitor and method of manufacturing same Thus, the present inventor experimentally produced and investigated a COB (Capacitor Over Bitline) structure as a means for solving this problem, as shown in FIGS. 1A ...
	Electrically erasable programmable logic device The preferred embodiment in accordance with the present invention will be discussed in detail with reference to FIG. 2(a) to FIG. 6. It is understood that the type of ...

0.014
Archive: All patents - Links Copyright (c)2006 Eipa-patents.org - All rights reserved