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Method of fabricating flash memory
| Details |
Inventors: Sheu, Yau-Kae;
Assignee: United Microelectronics Corp. (Hsinchu, TW)
Primary Examiner: Booth; Richard
Assistant Examiner:
Attorney, Agent or Firm:
A method for fabricating a flash memory. A bar-shaped first oxide layer and a bar-shaped first conductive layer are formed on a substrate. A mask layer is formed to cover one side of the first conductive layer from portions of the top surface of the first conductive layer to portions of the surface of the substrate. A second oxide layer is formed by oxidation on the remainder of the first conductive layer and the substrate from exposed portions of top surface of the first conductive layer to the substrate not covered by the mask layer. Meanwhile, the second oxide layer in the corner jointly formed by the first conductive layer and the substrate that are not covered by the mask layer is formed in a beak shape. After stripping the mask layer and portions of the second oxide layer, a doped region between the first conductive layers is formed. Then a dielectric layer and a second conductive layer are formed in sequence on the resulting structure. Subsequently, the second conductive layer, the dielectric layer and the first conductive layer are patterned, wherein the second conductive layer and the dielectric layer are continuous bars and perpendicular to the doped region. |
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DETAILED DESCRIPTION Therefore, the invention provides method of fabricating a flash memory, which has a high integration density for memory cells arrangement without the requirement of a device isolation structure between neighbor memory cell.
The invention provides a method of fabricating a flash memory by the following steps.
A first conductive layer covering a first oxide layer is formed on a substrate.
The first conductive layer and the first oxide layer are strip-like and extend along a first direction.
A mask layer is formed to extend from a part of a top surface of the first conductive layer along a sidewall there of towards a part of the substrate exposed next to the first conductive layer.
Therefore, a first side of the first oxide layer is covered by the mask layer, while a second side of the first oxide layer is exposed.
Using the mask layer as a mask, the exposed first conductive layer and the exposed substrate are oxidized into a second oxide layer.
As a consequence, the second side of the first oxide layer is expanded to form a bird's beak.
The mask layer, the second oxide layer are removed.
A doped region is formed in the substrate at each side of the first conductive layer.
A dielectric layer and a second conductive layer are formed on the first conductive layer and the substrate.
The dielectric layer, the second conductive layer, the first conductive layer and the first oxide layer are patterned to result in a strip-like controlling gate extending along a second direction perpendicular to the first direction and an island-like floating gate made of the patterned first conductive layer.
In accordance with the invention, since the thickness of the tunneling oxide layer close to the first bar-shaped doped region and that close to the second bar-shaped doped region are different, the tunneling oxide layer can bear with different voltages at two ends.
Thus, the disturbance between adjacent memory cells during programming can thereby be avoided.
Therefore, the flash memory provided by the invention can perform both programming and erasing by the FN tunneling operation without affecting the integration density, and the lifetime of the flash memory is further increased
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