 Semiconductor non-volatile memory device having a NAND cell structure |
| In light of the above, therefore, it is an object of the invention to provide an improved non-... |
|
| Light-emitting diode matrix with semi-insulating zones |
| What is claimed is: 1. A matrix of light-emitting diodes connected by conducting contacts and ... |
|
| Solid state light source for emitting light over a broad spectral band |
| According to the invention, there is provided a solid state light source for generating light in ... |
|
| Detecting lateral position of webs |
| I claim: 1. Apparatus for measuring the lateral position of a web as the web is fed along a ... |
|
| Web guide apparatus |
| OF THE PREFERRED EMBODIMENT Referring to FIG. 1 there is shown a diagrammatic illustration of a ... |
|
| Storage stable paper size composition containing ethoxylated lanolin |
| OF THE PREFERRED EMBODIMENTS The sizing compounds contemplated for use herein are the cyclic ... |
|
| Nanoscale modulation doping method |
| In accordance with the present invention, a nanoscale modulation doping method combines a focused ... |
|
| Gold recovery system |
| The invention is a process for recovering gold from dilute aqueous solution using an electrolytic ... |
|
| Method of patterning a thick resist layer of polymeric plastic |
| What is claimed is: 1. A method of forming in a first thick layer of a polymeric plastic overlying ... |
|
|
Method of forming high density flash memories with MIM structure
| Details |
Inventors: Wu, Shye-Lin;
Assignee:
Primary Examiner: Monin, Jr.; Donald L.
Assistant Examiner: Pham; Hoai V.
Attorney, Agent or Firm: Harness, Dickey & Pierce, P.L.C.
The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanical polishing the layer. A conductive layer is formed on the polysilicon layers. Subsequently, a silicon nitride layer deposited by jet vapor deposition (JVD) is formed on the conductive layer. A high k dielectric layer is next formed on the JVD nitride. A conductive layer to serve as control gate is subsequently formed on the high k dielectric layer. A patterning technique is used to pattern the layers. |
|
DETAILED DESCRIPTION The method of the present invention includes forming a gate oxide layer on a substrate.
Subsequently, a doped polysilicon layer is deposited on the gate oxide layer.
Then, a silicon nitride layer is deposited on the polysilicon layer to improve the resolution of lithography.
An etching step is used to etch the silicon nitride layer, polysilicon layer and gate oxide for forming a gate structure.
A dielectric layer is formed on the substrate.
Then, a polyoxide layer is simultaneously formed on side walls of the gate structure in the procedure.
Then, a silicon nitride layer is formed on the surface of the substrate.
Successively, the dielectric layer is etched back to form side wall spacers on the side walls of the gate structure.
Thus, only the portions of the oxide under the side wall spacers are left.
The source/drain structure of the device is fabricated using conventional masking and ion implantation steps.
A high temperature oxidation is performed to drive dopants deeper into the substrate.
The next step is to remove the side wall spacers and the oxide layer to expose a portion of the source and drain.
The silicon nitride layer and polyoxide layer are also stripped, thereby exposing the gate structure.
Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain.
A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide.
Next, a polysilicon layer is deposited on the patterned polysilicon and the oxide layer.
Subsequently, a chemical mechanical polishing (CMP) technique is used to polish the polysilicon layer.
The oxide at the top of the gate is removed during the CMP process.
A conductive layer is formed on the polysilicon layers.
The conductive layer can be selected from the group of TiN, WN, or TaN.
Subsequently, a silicon nitride layer deposited by jet vapor deposition (JVD) is formed on the conductive layer
|
|
Quantum Computing 
