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 Method of making a reverse self-aligned BIMOS transistor integrated circuit

Details
Inventors: Tsai, Nun-Sian; Tsai, Cliff Y.;
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. (Hsinchu, TW)
Primary Examiner: Chaudhuri; Olin
Assistant Examiner: Chaudhari; Chandra
Attorney, Agent or Firm: Saile; George O.

A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in the locations of the first element, the emitter for the bipolar and gate for the MOSFET, of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer. The second element is the base where the bipolar transistor is being formed and the source/drain where the field effect transistor is being formed. A uniform thickness conformal insulating layer is then deposited on the insulator layer over the conductive layer and oxidized substrate and preferentially removing the insulating layer from the horizontal surfaces and leaving a sidewall insulating layer upon the substantially vertical sidewalls. The integrated circuit is completed and the appropriate electrical contacts are made to the transistors of the IC.

DETAILED DESCRIPTION What is claimed is: 1.
The method of forming self-aligned field effect and bipolar transistors comprising: forming a heavily doped conductive layer of one conductivity type upon a monocrystalline semiconductor substrate of the opposite conductivity type to said one type; forming an insulator layer upon the surface of said conductive layer; forming openings with substantially vertical sidewalls through said conductive layer to said semiconductor substrate in at least the locations of first elements of said field effect transistors; heating the structure to form the heavily doped portions of second elements of said transistors of said one conductivity type by outdiffusing from said conductive layer; depositing a uniform thickness conformal insulating layer on said insulator layer over said conductive layer, the sidewalls of said opening and the substrate and then preferentially removing said insulating layer from the horizontal surfaces and leaving a sidewall insulating layer upon said substantially vertical sidewalls; said bipolar and MOS field effect transistors are located in different regions on said integrated circuit; said first elements are the emitters in the bipolar transistor regions, and the gate and channel in the MOS field effect regions; said second elements are the bases in bipolar regions and the sources/drains in the MOS field effect transistor regions; forming said gate and channel structures; forming said emitters and forming collectors where appropriate in said bipolar regions; and making electrical contacts to the elements of the said bipolar and field effect transistors to form said integrated circuit.
2.
The method of claim 1 wherein the conductive layer is polycrystalline silicon, the semiconductor substrate is silicon, and said polycrystalline silicon layer is N+ type conductivity imparting impurity and is doped by a phosphorous ion implantation process after its deposition.
3.
The method of claim 2 wherein the said polycrystalline silicon conductive layer includes a top portion of a refractory metal silicide



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