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Method of making deep sub-micron meter MOSFET with a high permitivity gate dielectric
| Details |
Inventors: Wu, Shye-Lin;
Assignee: Texas Instruments-Acer Incorporated (Hsinchu, TW)
Primary Examiner: Chaudhari; Chandra
Assistant Examiner:
Attorney, Agent or Firm: Merchant, Gould, Smith, Edell, Welter and Schmidt
The method of the present invention includes forming a silicon oxynitride layer on a substrate. Then, a dielectric layer with high permitivity is deposited by chemical vapor deposition on the silicon oxynitride layer. Subsequently, a rapid thermal process (RTP) anneal is performed in N.sub.2 O or NO ambient to reduce the dielectric leakage. A multiple conductive layer consisting of TiN/Ti/TiN is then formed on the dielectric layer. Then, the multiple conductive layer, the dielectric layer, and the silicon oxynitride layer are patterned to form gate structure. A plasma immersion is performed to form ultra shallow extended source and drain junctions. Side wall spacers are formed on the side walls of the gate structure. Next, an ion implantation is carried out to dope ions into the substrate. Next, a rapid thermal process (RTP) anneal is performed to form shallow junctions of the source and the drain. |
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DETAILED DESCRIPTION The method of the present invention includes forming a silicon oxynitride layer on a substrate.
The silicon oxynitride layer is preferably deposited by thermal oxidation in N.
sub.
2 O or NO ambient.
Then, a dielectric layer with high permitivity is deposited by chemical vapor deposition on the silicon oxynitride layer.
The dielectric layer is chosen from a group of TiO.
sub.
2, Ta.
sub.
2 O.
sub.
5, PZT or BST.
Subsequently, a rapid thermal process (RTP) anneal is performed at a temperature about 800 to 900 centigrade in N.
sub.
2 O or NO ambient to reduce the dielectric leakage.
A multiple conductive layer is then formed on the dielectric layer.
The multiple conductive layer is consisted of a TiN layer that is formed on the dielectric layer to serve as a barrier metal layer.
A metal layer is formed on the TiN layer for acting a gate of a transistor.
Preferably, the metal layer is formed of titanium or tungsten.
Next, an anti-refractive coating (ARC) layer is formed on the metal layer.
Then, the multiple conductive layer, the dielectric layer, and the silicon oxynitride layer are patterned to form gate structure.
A plasma immersion is performed to form ultra shallow extended source and drain junctions adjacent to the gate structure.
Side wall spacers are formed on the side walls of the gate structure.
Next, an ion implantation is carried out to dope ions into the substrate.
Next, a rapid thermal process (RTP) anneal is performed to form shallow junctions of the source and the drain.
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Quantum Computing 
