 Single poly memory cell and array |
| In light of the above, it is an object of the invention to provide an improved non-volatile ... |
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| Semiconductor device having sidewall insulating film |
| It is therefore an object of the present invention to prevent effectively the formation of fence-... |
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| Method of making split gate flash EEPROM cell by separating the tunneling region from the channel |
| What is claimed is: 1. A method manufacturing a flash EEPROM cell, comprising the steps of: forming ... |
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| Electrically erasable programmable logic device |
| The preferred embodiment in accordance with the present invention will be discussed in detail with ... |
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| Short channel IGBT with improved forward voltage drop and improved switching power loss |
| OF THE DRAWINGS Referring first to FIGS. 1 and 2, there is shown a portion of the active area of a ... |
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| Semiconductor non-volatile memory device having a NAND cell structure |
| In light of the above, therefore, it is an object of the invention to provide an improved non-... |
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| Light-emitting diode matrix with semi-insulating zones |
| What is claimed is: 1. A matrix of light-emitting diodes connected by conducting contacts and ... |
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Method of making dense vertical programmable read only memory cell structure
| Details |
Inventors: Yuan, Jack H.; Samachisa, Gheorghe; Guterman, Daniel C.; Harari, Eliyahou;
Assignee: SanDisk Corporation (Santa Clara, CA)
Primary Examiner: Chaudhari; Chandra
Assistant Examiner:
Attorney, Agent or Firm: Majestic, Parsons, Siebert & Hsue
A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed. |
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DETAILED DESCRIPTION These and additional objects are accomplished by the various aspects of the present invention, wherein, briefly and generally, according to one aspect, EPROM and EEPROM cells are reduced in size, and thus the density of cells on a given sized circuit chip is increased, by vertically orienting a significant proportion of the floating and control gate areas that provide the capacitive coupling between them.
This is accomplished, in a preferred embodiment, by first depositing a layer of thick oxide on the silicon substrate, and then forming vertically walled trenches in the oxide layer by anisotropically etching through to the substrate surface.
The cells are then constructed in the trenches and the thick oxide between trenches provides effective electrical isolation between adjacent memory cells.
In this way, sufficient coupling area between the floating gate and control gate is provided in order to maintain the necessary proportion of that capacitance relative to the total capacitive coupling with the floating gate for optimum performance.
This can be done without having to make an oxide dielectric layer between them so thin as to jeopardize the performance, life or yield of such devices.
This technique can be combined with an oxide/nitride sandwich dielectric to further increase the capacitive coupling, if so desired.
Essentially the entire structure of each memory cell is formed in a trench, the bottom of the trench being the channel between adjacent source and drain diffusions in the substrate.
The problem of wasted birds's beak areas that result from growing field oxide on the silicon surface is avoided by this structure and technique.
Optionally, the trenches can be reduced in width beyond that allowed by the resolution of current photolithography, by forming dielectric spacers against their sidewalls after etching the trench but before building the memory cell elements in it.
Further, the trenches may have their sidewalls sloped somewhat by initially performing an isotropic etch, which causes their top portion to be wider than the mask opening through which the etching is taking place, followed by an anisotropic etching step through the same mask opening that completes the trench
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Quantum Computing 
