Method of manufacturing semiconductor devices using trench isolation method that forms highly flat buried insulation film

DETAILED DESCRIPTION The object of this invention is to provide a method of manufacturing semiconductor devices whereby the insulating material can be buried in isolation trenches of different depths formed between circuit elements in such a way that the insulating performance and the surface flatness of the insulating material thus buried are high, and the parasitic capacitance of the wirings formed on the wide isolation region can be reduced.
This invention provides a method of manufacturing semiconductor devices which comprises the steps of: forming a first mask having an opening at a first region on the surface of a silicon body; etching the silicon body through the first mask to form a trench of a first depth in the first region; filling a first insulating material in the first-depth trench; forming a second mask having an opening which extends continuously from a second region adjacent to the first region on the surface of the silicon body to at least a part of the first region; etching the silicon body through the second mask to form a trench of a second depth only in the second region; and filling a second insulating material in the second-depth trench.
Since, with this method, after the first-depth trench is filled with the first insulating material, the second-depth trench is formed adjacent to the first trench and is filled with the second insulating material, it is possible to form an isolation region in which there are no complex steps at the bottom of the trenches and which has high surface flatness and insulation performance.
Therefore, the possibility of the wirings formed on the isolation region being broken due to uneven surface can be reduced.
Furthermore, by applying the filled-trench type isolation technique of this invention to the entire area of the isolation region other than the circuit element formation region, it is possible to suppress the parasitic capacitance of the upper wirings formed on the isolation region.
Particularly in a wide isolation region, the parasitic capacitance of the upper wirings on the isolation region can be substantially reduced by forming several strips of the first-depth trenches and also forming the second-depth trenches in the entire isolation region including the first-depth trenches