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Methods for forming a control gate apparatus in non-volatile memory semiconductor devices
| Details |
Inventors: Bui, Nguyen Duc;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Chaudhuri; Olik
Assistant Examiner: Mai; Anh Duy
Attorney, Agent or Firm:
Methods are provided to increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device. The methods effectively smooth out the top surface of the control gate layer, which allows for a subsequently formed silicide layer to be formed on the control gate layer without significant surface depressions. Significant surface depressions in either the control gate layer or the silicide layer can lead to cracking of the silicide layer during subsequent thermal processing of the semiconductor device. Thus the disclosed methods prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement. |
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DETAILED DESCRIPTION These needs and others are met by the present invention, which provides methods that increase the process control during the fabrication of semiconductor devices, and in particular, during the formation of the control gate configuration in a non-volatile memory semiconductor device.
In accordance with one aspect of the present invention, it has been found that, in certain semiconductor arrangements, the topology created by the space between adjacent floating gates (e.
g.
, 16a and 16b), can be so severe in shape (e.
g.
, deep and narrow) that the silicide layer 28 formed on the overlying control gate 26 often contains significant depressions over the space.
These significant depressions can lead to cracks in the silicide layer 28 during subsequent thermal processing of the semiconductor device, which tends to stress the silicide layer 28.
In accordance with one aspect of the present invention, the top of the conformal polysilicon layer, from which control gate 26 is formed, is smoothed to produce a more planar surface on which the silicide layer 28 is then formed.
Thus, regardless of the underlying topology the control gate 26 and suicide layer 28 will be substantially free of depressions.
Consequently, cracking of silicide layer 28 is substantially less likely to occur during the subsequent thermal processes.
Thus, in accordance with one embodiment of the present invention, a method is provided that includes the steps of forming at least two isolating regions, separated by an isolated region, within a substrate, forming a tunnel oxide on the top surface of the substrate and within the isolated region, and forming a floating gate on at least a portion of the tunnel oxide.
The method includes the steps of forming a dielectric layer on the floating gate and at least a portion of each of the two isolating regions.
The method further includes the steps of forming a control gate layer of a first thickness on the dielectric layer, and removing a portion of the control gate layer
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Quantum Computing 
