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Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device
| Details |
Inventors: Ramsbey, Mark T.; Chan, Vei-Han; Haddad, Sameer; Chang, Chi; Sun, Yu; Yu, Raymond;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Bowers; Charles
Assistant Examiner: Chen; Jack
Attorney, Agent or Firm:
Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly. |
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DETAILED DESCRIPTION These needs and others are met by the present invention, which in accordance with certain aspects, provides methods for fabricating semiconductor devices that effectively reduce the potential for electron trapping in a polysilicon or amorphous silicon feature in a semiconductor device by advantageously employing a nitrogen-rich region within the feature near the interface between the feature and an overlying dielectric layer.
Because the nitrogen-rich region significantly reduces the electron-trap density near this interface, the resulting semiconductor device is much less likely to be falsely programmed or otherwise significantly affected due to the subsequent release of trapped electrons.
In accordance with still further aspects of the present invention, improved fabrication techniques are employed to produce a high quality dielectric layer over the feature.
Thus, in accordance with certain embodiments of the present invention a method for forming a semiconductor device is provided.
The method includes forming a first dielectric layer, forming a first gate on the first dielectric layer, introducing nitrogen into the first gate, forming at least a portion of a second dielectric layer on the first gate with a high temperature oxide (HTO), and forming a first nitrogen-rich region within the first gate and substantially adjacent to the first dielectric layer, and a second nitrogen-rich region within the first gate and substantially adjacent the second dielectric layer.
In certain embodiments, the first gate includes either polysilicon and/or amorphous silicon.
In accordance with certain further embodiments of the present invention, the step of introducing nitrogen into the first gate includes implanting nitrogen ions into the first gate, the implanted nitrogen ions forming a first nitrogen concentration profile within the first layer, and the step of forming the first and second nitrogen-rich regions includes causing the first nitrogen concentration profile to be altered to form a second nitrogen concentration profile within the first gate
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Quantum Computing 
