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Details
Inventors: Gardner, Mark I.; Fulford, Jr., H. Jim;
Assignee: Advanced Micro Devices, Inc. ()
Primary Examiner: Niebling; John F.
Assistant Examiner: Lebentritt; Michael S.
Attorney, Agent or Firm: Daffer; Kevin L. Conley, Rose & Tayon, Kowert; Robert C.

An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions and source/drain regions. A dielectric layer, preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O.sub.2 ambient, or an H.sub.2 O ambient. Alternatively, the dielectric may be formed from a deposited oxide. Thereafter, a layer of polysilicon is formed on the dielectric layer and a plurality of "nitrogenated" polysilicon gates is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer. If implantation occurs after patterning of the polysilicon layer, nitrogen will be introduced into the source/drain regions and effect an increase in drive current without a corresponding increase in leakage current. In a presently preferred embodiment, a dose of between 5.times.10.sup.13 cm.sup.-2 and 1.times.10.sup.16 cm.sup.-2 is used for implanting the nitrogen bearing species and the species is distributed within the plurality of polysilicon gates such that the concentration of the nitrogen is greatest at approximately a midpoint within said gates. The semiconductor substrate may be subsequently annealed in an ambient maintained between approximately 900.degree. to 1100.degree. C. preferably using a rapid thermal anneal apparatus.

DETAILED DESCRIPTION The problems outlined above are in large part addressed by a method of fabricating an integrated circuit in which nitrogen is incorporated into the transistor gate at the interface between the gate and the underlying dielectric.
The nitrogen in the silicon gate fabricates the formation of stronger bonds with the underlying dielectric, preferably an oxide, and therefore results in improved transistor characteristics including higher resistance to gate oxide voltage breakdown.
The presence of nitrogen within the gate structure also inhibits the diffusion of impurities, especially boron, from the gate structure into the active region of the underlying transistor.
The reduction of dopant diffusion across the gate dielectric enables the formation of devices with thinner gate oxides and, therefore, superior operating characteristics.
In one embodiment of the present invention, the nitrogen is also incorporated into source/drain regions of the transistor.
In this embodiment, the presence of nitrogen within the source/drain regions results in an increase in drive current without a corresponding increase in leakage current.
In an embodiment in which it is desired to grow a dielectric over source/drain regions after implanting impurities into the source/drain regions, the nitrogen species are introduced into the gate structure prior to gate etch.
In this manner, introduction of the nitrogen will be blocked from entering the source/drain regions thereby allowing a subsequent oxidation of the source/drain region.
Broadly speaking, the present invention contemplates a method of fabricating an integrated circuit.
The method comprises the providing of a semiconductor substrate that has a P-well region and an N-well region.
The N-well region is laterally displaced from the P-well region.
Both the N-well and the P-well regions include channel regions and source/drain regions.
A dielectric layer is formed on an upper surface of the semiconductor substrate.
Thereafter, a plurality of "nitrogenated" silicon gates is formed on the dielectric layer over the channel regions



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