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| Method of making split gate flash EEPROM cell by separating the tunneling region from the channel |
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| Electrically erasable programmable logic device |
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| Short channel IGBT with improved forward voltage drop and improved switching power loss |
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| Semiconductor non-volatile memory device having a NAND cell structure |
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Non-volatile memory structure including protection and structure for maintaining threshold stability
| Details |
Inventors: Fang, Hao; Haddad, Sameer; Chang, Chi;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Limanek; Robert P.
Assistant Examiner:
Attorney, Agent or Firm: Benman Collins & Sawyer
An improved nonvolatile memory device is provided, in which the threshold voltage variations (V.sub.ts) and transconductance degradation are significantly reduced. The NVM includes protection structure for limiting the process induced damage incurred during the manufacturing process. The protection structure is utilized to provide reliable and stable dielectrical characteristics for the NVM device. The protection structure is easy to implement and will not affect the conventional NVM performance. |
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DETAILED DESCRIPTION It has been discovered that the V.
sub.
ts instability is due to plasma induced charging damage on the dielectric layers of a nonvolatile memory device.
Accordingly, in a first aspect, a non-volatile memory (NVM) comprises a metal layer,a first polysilicon (p) layer coupled to the metal layer, and a dielectric layer coupled to the first p layer.
The NVM further includes a second p-layer coupled to the dielectric layer, a tunnel oxide region coupled to the second p-layer, a source region coupled to the tunnel oxide region, and a drain region coupled to the tunnel oxide region.
The NVM in accordance with the present invention further includes protection means coupled to the metal layer for preventing plasma induced damage to the dielectric layer.
In another aspect, the protection means comprises a polysilicon or metal fuse coupled between the metal layer and a p-substrate.
In yet another aspect, the protection means comprises a diode coupled to the metal layer.
In yet another aspect, the protection means comprises a transistor coupled to the metal layer.
In a final aspect of the present invention, the protection means comprises a first diode coupled to the metal layer, a P well coupled to the first diode, a second diode coupled to the metal layer, and a N well coupled to the second transistor.
The protection means in accordance with the present invention is utilized advantageously to prevent a process-induced charge build up and hence the stress voltage on the dielectric layers of the NVM and thereby provides for V.
sub.
ts stability, high G.
sub.
m and better reliability.
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Quantum Computing 
