Nonvolatile ferroelectric memory and a method of manufacturing the same

DETAILED DESCRIPTION Therefore, the present invention is directed to solve the problems of the conventional FRAM and is to provide a nonvolatile ferroelectric memory device having SWL structure without any separated cell plate lines.
To achieve an object of the present invention, the nonvolatile ferroelectric memory device according to the present invention includes a main cell array arranged in columns of an even number; a reference cell array arranged in two columns; a plurality of cell array blocks in which a plurality of pairs of said main cell array and said reference cell array are arranged; SWL word line driver in parallel to said column; and control block connected between both ends of said column so as to control other cell array block neighboring with said cell array block.
To achieve another object of the present invention, the nonvolatile ferroelectric memory device according to the present invention includes a first control pulse generator including a first logic arithmetic unit which receives control signals which include both preparatory signals (SAP and SAN) to control the sense amplifier and the predecoded Z address signals (Z.
sub.
-- Add3 and Z.
sub.
-- Add4) as its input signals and generates sense amplifier control signals (SAP.
sub.
-- C, SAN.
sub.
-- C) and equi-potential control signals (C3N.
sub.
-- C, C3P.
sub.
-- C) as its output signal and a second logic arithmetic unit which receives the predecoded Z address signals (Z.
sub.
-- Add3 and Z.
sub.
-- Add4) as its input signal and generates C1P.
sub.
-- T, C1N.
sub.
-- T, C2P.
sub.
-- T, C2N.
sub.
-- T, and C3N.
sub.
-- T signals to control the bit line connection and the level adjustment as its output signals; a second control pulse generator which receives signals including the write enable signal (WEBpad) and generates control signals (C4P.
sub.
-- T, C4N.
sub.
-- T) for column selection; and a third control pulse generator which receives Y address transition detection signal (Y.
sub.
-- ATD) and generates preparatory SWL driving signals (PS1