 Method for suppressing boron penetration in PMOS with nitridized polysilicon gate |
| OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a preferred embodiment according to the present ... |
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| Selective diffusion process for forming both n-type and p-type gates with a single masking step |
| In accordance with this invention, both first and second conductivity type regions are formed in a ... |
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| Nitrogenated gate structure for improved transistor performance and method for making same |
| The problems outlined above are in large part addressed by a method of fabricating an integrated ... |
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| Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening |
| The present invention provides a method for hardening of gate oxide without forming low boron ... |
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| Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control |
| The present invention is directed to a SOI MOSFET device that includes a dynamic threshold voltage ... |
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| Heating method of semiconductor wafer |
| With the foregoing in view, the present invention has as its object the provision of a heating ... |
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| Inverted-design optical microscope |
| In view of the above mentioned circumstances, a primary object of the present invention is to ... |
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Planar interconnect for integrated circuits
| Details |
Inventors: Wu, Andrew L.;
Assignee: Digital Equipment Corporation (Maynard, MA)
Primary Examiner: Lusignan; Michael R.
Assistant Examiner:
Attorney, Agent or Firm: Cesari and McKenna
An integrated circuit having a plurality of devices on a substrate is disclosed, wherein a plurality of metallization layers, separated by a plurality of insulating layers, are used to interconnect the devices. Each metallization layer is recessed in an upper portion of a corresponding dielectric layer. A metallization layer is connected to a lower one, or, in the case of the first metallization layer, to the devices, by solid contacts extending through via windows in the lower portion of the corresponding dielectric layer. A method of manufacturing such an integrated circuit is also disclosed, whereby each layer is formed in two steps. First, the lower portion of the insulating layer is deposited, the contact pattern opened and the vias windows filled with metal to provide contacts even with the top surface of the lower portion of the insulating layer. Then, the upper portion of the insulating layer is deposited over the lower portion, the metallization pattern opened, and the pattern filled with metal up to and even with the top surface of the upper portion of the insulating layer. The metal filling step is produced by depositing a metal layer over the corresponding portion of opened insulating layer, masking the opened regions and selectively and directionally removing the unprotected metal layer. |
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DETAILED DESCRIPTION It is an object of the subject invention to provide an integrated circuit having a dense multilayer metallization.
More specifically, it is an object of this invention to provide an improved co-planar composite electrical conductor-insulator layer which avoids the problems of the prior art.
It is a further object of the present invention to provide a method to fabricate dense multilayer metallization for integrated circuits.
The present invention provides patterns recessed by anistropic reactive ion etching (referred to as PRAIRIE) for a dense multilayer metallization interconnecting a plurality of semiconductor devices in a semiconductor substrate.
A first metallization layer is recessed on an upper portion of a first insulating layer disposed over the substrate containing said plurality of devices.
The upper surface of the first metallization layer is aligned with the upper surface of the insulating layer.
The metallization layer is connected to selected devices by solid contacts extending through windows in a lower portion of the insulating layer.
A second insulating layer is disposed over the first, and a second metallization layer is recessed in an upper portion therein and connected, through contacts provided in a lower portion of the second insulating layer, to the first metallization layer in selected regions.
Any desired number of additional metallization layers may be provided, each recessed within a corresponding insulating layer, and connected to a lower one by contacts extending through windows in the corresponding insulating layer.
The present invention also provides for a method of manufacturing such a multilayer metallization integrated circuit.
The present method starts with a substrate in which a plurality of devices have been fabricated by any conventional method.
It then provides for the fabrication of a substantially planar surface for each insulating layer, and corresponding metallization layer recessed therein, in two steps.
First, a first portion of the insulating layer is deposited and metal contacts are formed therein, then a second portion of the insulating layer is deposited on top of the first and the metallization layer is formed therein
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Quantum Computing 
