Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control

DETAILED DESCRIPTION The present invention is directed to a SOI MOSFET device that includes a dynamic threshold voltage control scheme, which is suitable for both high-performance, i.
e.
, circuit/system active periods, and low-power, i.
e.
, circuit/system idle periods, applications.
Specifically, the present invention provides a SOI MOSFET device comprising a polysilicon back-gate region which controls the threshold voltage of the front-gate.
NMOS and PMOS back-gates are also present which are switched independently of each other and the back-gate.
For high-performance and low-power applications, the threshold voltage would be raised during system/circuit idle periods to reduce the static leakage current, and lowered during circuit/system active periods to achieve high-performance.
In the device aspect of the present invention, a SOI MOSFET device is provided that comprises: an implanted back-gate region located atop an oxide layer, wherein a surface portion of said implanted back-gate region includes a back-gate oxide formed thereon; a body region located atop said back-gate oxide; a gate dielectric located atop a surface portion of said body region; and a polysilicon gate located atop a portion of said gate dielectric.
The present invention also provides a method of fabricating the above-mentioned SOI MOSFET device.
The inventive method utilizes processing steps that are compatible with conventional CMOS processes.
Specifically, the method of the present invention comprises the steps of: providing a structure including at least a back-gate oxide located atop a Si-containing layer, said Si-containing layer is a component of a SOI wafer; forming alternating regions of back-gate-STI and first polysilicon atop said back-gate oxide; forming a second polysilicon layer atop said alternating regions of back-gate-STI and first polysilicon; implanting a back-gate region into said polysilicon layers; forming an oxide layer on said second polysilicon layer; bonding a holding-substrate wafer to said oxide layer and flipping the bonded structure to expose layers of said SOI wafer; removing selective layers of said SOI wafer stopping on said Si-containing layer; converting a portion of said Si-containing layer into a body region; and forming a gate dielectric and a polysilicon gate atop said body region