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Process-for-forming-a-buried-drain-or-collector-region-in-monolithic-semiconductor-devices

Photosensitive resin composition containing pullulan or esters thereof

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I claim: 1. An ester as a composition of matter, which is soluble in an aqueous solution of a base ...

Process for forming a buried drain or collector region in monolithic semiconductor devices

Details

Inventors: Zambrano, Raffaele;
Assignee: SGS Thomson Microelectronics, S.r.l. (Agrate Brianza, IT)
Primary Examiner: Chaudhuri; Olik
Assistant Examiner: Pham; Long
Attorney, Agent or Firm:

The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage by the implantation of a buried gate region in a first epitaxial layer after the formation of said epitaxial layer. These buried gate regions high dopant concentrations where the dopants have low diffusion coefficients. These low diffusive dopants permit more accurate and form defined buried gate regions than current formation techniques utilizing formation of buried gate regions implemented in the substrate where these gate regions contain highly diffusive dopants.

DETAILED DESCRIPTION The process in accordance with the invention aims at overcoming the above drawbacks.
A first innovative process embodiment comprises the following steps: growing on a substrate having a first type of conductivity a first epitaxial layer having the same type of conductivity; forming in said first epitaxial layer at least one region with high concentration of dopant of the same type of conductivity as the substrate and low diffusion coefficient and which joins with said substrate and is designed to constitute the buried drain or collector region of the power transistor.
In accordance with other versions the process in accordance with the invention is characterized in that it comprises the following steps: growing on a substrate of a first type of conductivity a first epitaxial layer having conductivity of the same or opposite type; forming in said first epitaxial layer at least one region with high concentration of a dopant of the same type of conductivity as the substrate and high diffusion coefficient and which joins with said substrate and is designed to constitute the buried drain or collector region of the power transistor.

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