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 Process for self aligning a source region with a field oxide region and a polysilicon gate

Details
Inventors: Tang, Daniel N.; Lu, Wen-Juei;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Hearn; Brian E.
Assistant Examiner: Chaudhari; C.
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman

A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

DETAILED DESCRIPTION A method and apparatus for self-aligning a source diffusion to field oxide regions, poly word lines and gate edges is disclosed.
In the following description, numerous specific details are set forth, such as specific materials, devices, process steps, dimensions, etc.
, in order to provide a thorough understanding of the present invention.
It will be obvious, however, to one skilled in the art that these specific details need not be employed to practice the present invention.
In other instances, well-known processing steps and device configurations are not described in detail in order not to unnecessarily obscure the present invention.
The present invention discloses a method and an apparatus to allow a source diffusion node of a semiconductor device to be defined by a self-aligned method to edges of field oxide regions, poly word lines and gate edges of the device.
This method and apparatus saves silicon real estate by reducing spaces reserved for layer registration, field oxide bird's beak encroachment and lithographic/field oxidation induced isolation corner rounding.
This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.
With reference to the drawings, FIG.
5 illustrates a top view of a portion of a memory device formed i accordance with the present invention.
In the preferred embodiment, field oxide regions 31 and 33 are formed by growing oxide between parallel rows of nitride regions 18 to form the field oxide regions 31 and 33 as continuous lines across the source line 12, rather than as separate field oxide regions (reference nos.
13, 15, 17 and 19 in FIG.
1) formed in the openings of a lattice-work of nitride regions 18 as is known in the prior art (and as shown in FIG.
1).
A layer of polysilicon is then deposited over the field oxide regions 31 and 33.
After placing a photoresist mask over the polysilicon, the portions of the polysilicon left exposed are etched away



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