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Selective diffusion process for forming both n-type and p-type gates with a single masking step
| Details |
Inventors: Choi, Jeong Yeol;
Assignee: Integrated Device Technology, Inc. (Santa Clara, CA)
Primary Examiner: Chaudhari; Chandra
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill, Morrill, MacPherson, Franklin & Friel
First and second conductivity type regions are produced in a polysilicon layer using only a single masking step. In one embodiment, the polysilicon layer is doped to a first conductivity type. A first oxide layer is then formed and patterned over the polysilicon layer to cover a first region and expose a second region of the polysilicon layer. The exposed second region of the polysilicon layer is then counter-doped, with the first oxide layer acting as a mask to prevent counter-doping of the underlying first region of the polysilicon layer. In accordance with the present invention, n-channel devices with n-type or p-type polysilicon gates and p-channel devices with p-type or n-type polysilicon gates can be formed without having to add a single process step. Thus, n-channel and p-channel devices with two different threshold voltages can be realized without adding a single process step. |
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DETAILED DESCRIPTION In accordance with this invention, both first and second conductivity type regions are formed in a single layer of polysilicon using a single masking step.
In one embodiment, a polysilicon layer is doped to a first conductivity type with a first dopant.
A first oxide layer is formed and patterned over a first region of the polysilicon layer thus exposing a second region of the polysilicon layer.
The exposed second region of the polysilicon layer is then counter-doped to a second conductivity type opposite the first conductivity type with a second dopant.
In one embodiment, the polysilicon layer is doped to the first conductivity type through ion implantation, and the second region of the polysilicon layer is counter-doped to the second conductivity type using dopant diffusion, with the first oxide layer masking the underlying first region of the polysilicon layer to prevent counter-doping of this first region.
In another embodiment, the first oxide layer is patterned by first depositing and patterning a photoresist mask to cover a first region and to expose a second region of the first oxide layer.
Then, the exposed second region of the first oxide layer is stripped.
Then, the photoresist mask is stripped.
In other embodiments, the first dopant is boron obtained from diboron hexahydride (B.
sub.
2 H.
sub.
6) and the second dopant is phosphorus obtained from phosphorus oxychloride (POCl.
sub.
3).
In alternative embodiments, a silicon substrate is doped to form an n-well and a p-well.
An insulating layer is formed on the silicon substrate and the polysilicon layer is deposited on the insulating layer.
A first conductivity type region and a second conductivity type region are formed in the polysilicon layer using the single masking step method as described above, where the first and second conductivity types are n-type and p-type.
The polysilicon regions are patterned to form n-type and p-type polysilicon gates.
Source/drain regions are formed in the n-well and the p-well thereby forming p-channel and n-channel devices
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Quantum Computing 
