Semiconductor integrated circuit device with a high tolerance against abnormally high input voltage

DETAILED DESCRIPTION I claim: 1.
A semiconductor integrated device having a high tolerance against abnormally high input voltages, comprising: a semiconductor substrate having a first conductivity type; an input electrode formed on said semiconductor substrate; an input stage of said semiconductor integrated device formed on said semiconductor substrate and including a first MIS transistor comprising a gate insulator layer, a first gate electrode, and a first source region and a first drain region each having a second conductivity type being the opposite of said first conductivity type, said first source region or said first drain region being electrically connected to said input electrode; an internal circuit of said semiconductor integrated device formed on said semiconductor substrate and including a second MIS transistor comprising a second gate electrode, a second source region, and a second drain region, each of said second source region and said second drain region having said second conductivity type, said second gate electrode being electrically connected to said first source region or said first drain region not connected to said input electrode; and another internal circuit of said semiconductor device operatively connected to said first gate electrode; said first source region or said first drain region connected to said input electrode has a depth greater than the depth of said second source or drain region, has a depth greater than said first source region or said first drain region not connected to said input electrode, and has an impurity concentration varying in a first direction perpendicular to the surface of said semiconductor substrate from a first concentration at the surface of said semiconductor substrate to a second concentration lower than said first concentration and at respective levels along said first direction being substantially uniform throughout said first source or drain region in a direction parallel to the surface to the surface of said semiconductor substrate, whereby said first gate insulation layer is prevented from destruction due to said abnormally high input voltages applied to said input electrode