Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device

DETAILED DESCRIPTION An object of the invention is to provide a process for forming a layer of polycrystalline silicon having both p-type and n-type conductivity using a single mask step.
This and other objects of the invention are realized by first forming n- and p-wells in a semiconductor substrate, and forming layers of oxide (such as gate oxide) and polycrystalline silicon over the substrate.
Next, a nonoxidizable dielectric such as Si.
sub.
3 N.
sub.
4 is patterned on top of the polycrystalline silicon so as to cover the n-well in the substrate.
The exposed poly is doped to an n-type conductivity, for example by implantation or by diffusion/deposition.
The poly over the p-wells then becomes n-type.
The n-type poly is then oxidized with the amount of oxidization controlled so as to leave a sufficient amount of n-type poly unoxidized over the p-wells.
A poly thickness of 1,000 .
ANG.
is known to be sufficient, although thicknesses, either thicker or thinner, are also possible.
The poly over the n-wells is not oxidized due to the patterned nonoxidizing dielectric layer which was deposited earlier in the process as described above.
The remaining nonoxidizing dielectric patterned layer is now removed without removing any significant amount of oxide or poly.
The poly over the n-wells is then doped to a p-type conductivity by ion implantation or by diffusion/deposition.