Use of implanted ions to reduce oxide-nitride-oxide (ONO) etch residue and polystringers

DETAILED DESCRIPTION The present invention provides for a method of manufacturing a memory cell which prevents the formation of poly stringers resulting from an ONO fence.
ONO fences typically result from an anisotropic etching step which leaves an ONO fence on sidewalls of a poly I layer.
As noted above, the ONO fence can result in the formation of poly stringers which may short adjacent memory cells.
The present invention removes the need for an initial poly I etching step which in turn avoids formation of an ONO fence and which in turn prevents polystringers from forming.
According to the present invention, a poly I layer is masked to pattern future memory cells.
In other words, a poly I mask is configured to isolate floating gate regions of memory cells in a desired manner.
The unmasked portions of the poly I layer are transformed into insulating portions (e.
g.
, silicon oxide, silicon dioxide, silicon nitride, silicon oxy-nitride, etc.
) by a suitable technique in accordance with the present invention.
The resulting insulating portions serve to isolate the floating gates of patterned memory cells from one another.
The present invention eliminates the need to perform an initial etch of the poly I layer as is done conventionally, which in turn eliminates formation of an ONO fence and subsequent formation of poly stringers.
More specifically, since the poly I layer is not etched, ONO is never formed adjacent a row or column of poly I because the area between rows or columns of poly I is occupied by an insulating medium (e.
g.
, poly I transformed into silicon dioxide).
In the present invention, the ONO is deposited on a wafer surface that is free of changes in height that occur over angles greater that .
about.
60.
degree.
.
That is, changes in the height of the surface of the wafer result from gentle undulations rather than from substantially abrupt 90.
degree.
steps.
In particular, since there is no initial poly I etch step there is no formation of gaps between poly I rows as which result using conventional memory cell fabrication techniques