Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Quantum Computing Vertical-semiconductor-device-and-method-of-manufacturing-the-same

 Method of depositing thin nitride layer on gate oxide dielectric
The present invention is a gate structure in a transistor and method for fabricating the structure. ...


 Method of forming high density flash memories with MIM structure
The method of the present invention includes forming a gate oxide layer on a substrate. S...


 Method for fabricating a capacitor
The invention provides a method for fabricating a capacitor. A first metal layer is formed on a ...


 4-Aminothiazole
What is claimed is: 1. 4-Aminothiazole and its acid addition salts. 2. The compound of claim 1 ...


 Single poly memory cell and array
In light of the above, it is an object of the invention to provide an improved non-volatile ...


 Etox cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current
An ETOX cell formed in a semiconductor substrate is disclosed. The ETOX cell comprises: a p-well ...


 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
Our preceding patent application has proposed the use of storage elements of one flash memory for ...


 Semiconductor device having sidewall insulating film
It is therefore an object of the present invention to prevent effectively the formation of fence-...


 Method of making split gate flash EEPROM cell by separating the tunneling region from the channel
What is claimed is: 1. A method manufacturing a flash EEPROM cell, comprising the steps of: forming ...


 Semiconductor memory device having word line conductors provided at lower level than memory cell capacitor and method of manufacturing same
Thus, the present inventor experimentally produced and investigated a COB (Capacitor Over Bitline) ...


 Vertical semiconductor device and method of manufacturing the same

Details
Inventors: Konishi, Yoshinori;
Assignee: Fuji Electric Co. (JP)
Primary Examiner: Jackson; Jerome
Assistant Examiner: Kelley; Nathan K.
Attorney, Agent or Firm: Rossi & Associates

A vertical semiconductor device incorporates a semiconductor laminar structure including a semiconductor substrate of a first conductive type having a relatively high impurity concentration, a first semiconductor layer of the first conductive type laminated on the semiconductor substrate and having a relatively low impurity concentration, and a second semiconductor layer of the first conductive type laminated on the first semiconductor layer and having an even lower impurity concentration. A trench is formed in the semiconductor laminar structure to extend through the second semiconductor layer into the first semiconductor layer. A source region of the first conductive type is formed in a surface layer of the second semiconductor layer and the trench is filled with a gate electrode. A source electrode is formed on the source region and a drain electrode is formed on a rear surface of the semiconductor substrate.

DETAILED DESCRIPTION In the light of the above problems, it is an object of the present invention to provide an accumulation type field-effect transistor which has a high withstand voltage and suffers from a reduced leakage current.
The above object may be accomplished according to the principle of the present invention, which provides a vertical semiconductor device comprising: a semiconductor laminar structure including a semiconductor substrate of a first conductive type having a first impurity concentration, a first semiconductor layer of the first conductive type laminated on the semiconductor substrate and having a second impurity concentration lower than the first impurity concentration, and a second semiconductor layer of the first conductive type laminated on the first semiconductor layer and having a third impurity concentration lower than the second impurity concentration, the semiconductor laminar structure having a trench extending from a surface thereof through the second semiconductor layer to reach the first semiconductor layer; a source region of the first conductive type formed in a surface layer of the second semiconductor layer and having a fourth impurity concentration higher than the third impurity concentration; a gate electrode filling the trench through a gate oxide film; an insulating film formed on the gate electrode; a source electrode formed on a surface of the source region of the first conductive type; and a drain electrode formed on a rear surface of the semiconductor substrate of the first conductive type.
In the semiconductor device constructed as described above according to the present invention, the trench extends from the surface of the semiconductor laminar structure into the first semiconductor layer through the second semiconductor layer.
In this arrangement, the first semiconductor layer carries a part of the voltage applied between the source and drain electrodes, thereby reducing a voltage to be carried by the gate oxide film.
This eventually leads to an improved withstand voltage of the device



Related patents
  High voltage semiconductor device capable of increasing a switching speed
OF THE INVENTION Embodiments of the present invention will now be described with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a cross-sectional ...
  Method of making MOS transistor having improved oxynitride dielectric
In accordance with the invention, a silicon oxide dielectric is grown in a nitrous oxide (N.sub.2 O) environment and then nitrided in an anhydrous ammonia (NH.sub.3) ...
  Non-volatile memory structure including protection and structure for maintaining threshold stability
It has been discovered that the V.sub.ts instability is due to plasma induced charging damage on the dielectric layers of a nonvolatile memory device. Accordingly, in a ...
  Method of making dense vertical programmable read only memory cell structure
These and additional objects are accomplished by the various aspects of the present invention, wherein, briefly and generally, according to one aspect, EPROM and EEPROM ...
  Method of fabricating a high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory
What is claimed is: 1. A method of fabricating a dielectric structure in a non-volatile memory, comprising the steps of: (A) providing a first polysilicon layer; (B) ...
  Methods for forming a control gate apparatus in non-volatile memory semiconductor devices
These needs and others are met by the present invention, which provides methods that increase the process control during the fabrication of semiconductor devices, and in ...
  Dielectric device
In view of the present need as described above, an object to the present invention is to provide a dielectric device having a high permittivity and sufficient dielectric ...
  Method of making deep sub-micron meter MOSFET with a high permitivity gate dielectric
The method of the present invention includes forming a silicon oxynitride layer on a substrate. The silicon oxynitride layer is preferably deposited by thermal oxidation ...
  High dielectric TiO.sub.2 -SiN composite films for memory applications
One object of the present invention is to provide a method for fabricating a high dielectric composite structure for use in advanced memory applications. Another object ...
  MOSFET with a high permitivity gate dielectric
The method of the present invention includes forming a silicon oxynitride layer on a substrate. The silicon oxynitride layer is preferably deposited by thermal oxidation ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved