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Results: 1-30 of 2287
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Semiconductor device with current detecting function
Accordingly, it is an object of the present invention to provide a semiconductor device having a current detecting function which has been developed for obviating the above-mentioned problems to produ... Read More
Inventors: Tokura, Norihito; Kuno, Hironari; Ito, Hiroyasu; Saito, Hirohiko; Hara, Kunihiko;, Assignee: Nippondenso Co., Ltd. (Kariya, JP) |
Method for manufacturing semiconductor device
It is an object of the present invention to provide a method for manufacturing a semiconductor device which solves the above-mentioned problems and with which a GaAs MESFET and an integrated circuit u... Read More
Inventors: Yoshida, Kazuhiro;, Assignee: Murata Manufacturing Co., Ltd. (JP) |
Planar interconnect for integrated circuits
It is an object of the subject invention to provide an integrated circuit having a dense multilayer metallization. More specifically, it is an object of this invention to provide an improved co-planar... Read More
Inventors: Wu, Andrew L.;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Logic circuit using vertically stacked heterojunction field effect transistors
The advantages of the present invention are achieved by a heterojunction field effect transistor structure having vertically stacked complementary devices. A P-channel quantum well and an N-channel qu... Read More
Inventors: Zhu, X. Theodore; Abrokwah, Jonathan K.; Goronkin, Herbert; Ooms, William J.; Shurboff, Carl L.;, Assignee: Motorola, Inc. (Schaumburg, IL) |
Method of making substantially linear field-effect transistor
The device and the method of making the same discussed in this application has substantial commonality with the devices, and method of making those devices, as discussed in U.S. Pat. No. 5,041,393 by... Read More
Inventors: Green, Jr., Donald R.;, Assignee: AT&T Bell Laboratories (Murray Hill, NJ) |
Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts
Briefly stated, the scope of the present invention encompasses a III-V complementary semiconductor device employing compatible ohmic contacts. Specifically, a preferred embodiment includes an N-channe... Read More
Inventors: Abrokwah, Jonathan K.; Huang, Jenn-Hwa; Ooms, William J.;, Assignee: Motorola, Inc. (Schaumburg, IL) |
SiC/111-V-nitride heterostructures on SiC/SiO.sub.2 /Si for optoelectronic devices
These problems and needs will be met in accordance with a preferred embodiment of the invention by converting 100% of a 100-500 .ANG. layer of Si of a silicon-on-insulator wafer to 3C SiC with propane... Read More
Inventors: Soref, Richard A.; Namavar, Fereydoon;, Assignee: The United States of America as represented by the Secretary of the Air (Washington, DC) |
Separation of thin films from transparent substrates by selective optical processing
The invention may be summarized as a method of transferring a crystalline film from a growth substrate to an acceptor substrate. The film of one composition is grown on a substrate of another composit... Read More
Inventors: Cheung, Nathan W.; Sands, Timothy D.; Wong, William S.;, Assignee: The Regents of the University of California (Oakland, CA) |
Apparatus comprising refractive means for elections
OF SOME EXEMPLARY EMBODIMENTS Before describing some currently preferred embodiments we will derive expressions describing the effect of a potential step on the propagation of a ballistic electron in... Read More
Inventors: Baldwin, Kirk W.; Pfeiffer, Loren N.; Spector, Joseph; Stormer, Horst L.; West, Kenneth W.;, Assignee: AT&T Bell Laboratories (Murray Hill, NJ) |
Nonvolatile ferroelectric memory and a method of manufacturing the same
Therefore, the present invention is directed to solve the problems of the conventional FRAM and is to provide a nonvolatile ferroelectric memory device having SWL structure without any separated cell ... Read More
Inventors: Kang, Hee Bok;, Assignee: LG Semicon Co., Ltd. (Cheongju, KR) |
Filamentary electron-emission device having self-aligned gate or/and lower conductive/resistive region
What is claimed is: 1. A structure comprising: a substrate for providing structural support; a lower electrically conductive region comprising a group of generally parallel highly conductive lines sit... Read More
Inventors: Macaulay, John M.; Searson, Peter C.; Duboc, Jr., Robert M.; Spindt, Christopher J.;, Assignee: Candescent Technologies Corporation (San Jose, CA) |
Methods of forming materials within openings, and method of forming isolation regions
In one aspect, the invention encompasses a method of forming a material within an opening. An etch-stop layer is formed over a substrate. The etch-stop layer has an opening extending therethrough to e... Read More
Inventors: Moore, John T.; Blalock, Guy T.;, Assignee: Micron Technology, Inc. (Boise, ID) |
PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OF OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT
The invention comprises a process for inhibiting the passage of dopant from a thin polysilicon gate electrode into a thin gate oxide beneath the gate electrode, and thereby also inhibiting the further... Read More
Inventors: Aronowitz, Sheldon; Haywood, John; Kimball, James P.; Puchner, Helmut; Kapre, Ravindra Manohar; Eib, Nicholas;, Assignee: LSI Logic Corporation (Milpitas, CA) |
Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device
An object of the invention is to provide a process for forming a layer of polycrystalline silicon having both p-type and n-type conductivity using a single mask step. This and other objects of the inv... Read More
Inventors: Maddox, III, Roy L.; Mathews, Viju K.; Fazan, Pierre C.;, Assignee: Micron Semiconductor, Inc. (Boise, ID) |
Method for suppressing boron penetration in PMOS with nitridized polysilicon gate
OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a preferred embodiment according to the present invention includes the following steps: 1) in a condition that rates of O.sub.2 volume over time and N... Read More
Inventors: Lin, Yung-Hao; Lai, Chao-Sung; Lee, Chung-Len; Lei, Tan-Fu;, Assignee: National Science Council (Taipei, TW) |
Selective diffusion process for forming both n-type and p-type gates with a single masking step
In accordance with this invention, both first and second conductivity type regions are formed in a single layer of polysilicon using a single masking step. In one embodiment, a polysilicon layer is do... Read More
Inventors: Choi, Jeong Yeol;, Assignee: Integrated Device Technology, Inc. (Santa Clara, CA) |
Nitrogenated gate structure for improved transistor performance and method for making same
The problems outlined above are in large part addressed by a method of fabricating an integrated circuit in which nitrogen is incorporated into the transistor gate at the interface between the gate an... Read More
Inventors: Gardner, Mark I.; Fulford, Jr., H. Jim;, Assignee: Advanced Micro Devices, Inc. () |
Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer
The problems outlined above are in large part solved by an improved transistor configuration. The transistor can be either a p-channel or n-channel transistor. The transistor hereof is classified as a... Read More
Inventors: Kadosh, Daniel; Hause, Fred N.; Cheek, Jon D.;, Assignee: Advanced Micro Devices, Inc. () |
Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device
These needs and others are met by the present invention, which in accordance with certain aspects, provides methods for fabricating semiconductor devices that effectively reduce the potential for elec... Read More
Inventors: Ramsbey, Mark T.; Chan, Vei-Han; Haddad, Sameer; Chang, Chi; Sun, Yu; Yu, Raymond;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening
The present invention provides a method for hardening of gate oxide without forming low boron concentration regions in polysilicon at the gate oxide-polysilicon interface. This is accomplished by a pr... Read More
Inventors: Wang, Shiuh-Luen; Yao, Chiang-Sheng; Yeh, Wen-Chin;, Assignee: LSI Logic Corporation (Milpitas, CA) |
Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control
The present invention is directed to a SOI MOSFET device that includes a dynamic threshold voltage control scheme, which is suitable for both high-performance, i.e., circuit/system active periods, and... Read More
Inventors: Dennard, Robert H.; Haensch, Wilfried E.; Hanafi, Hussein I.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Heating method of semiconductor wafer
With the foregoing in view, the present invention has as its object the provision of a heating method of a semiconductor wafer which method permits to achieve a selective heating of a wafer region to ... Read More
Inventors: Arai, Tetsuji; Mimura, Yoshiki;, Assignee: Ushio Denki Kabushiki Kaisha (Tokyo, JP) |
Inverted-design optical microscope
In view of the above mentioned circumstances, a primary object of the present invention is to provide an inverted-design optical microscope simple in the formation and capable of being manufactured at... Read More
Inventors: Inoue, Yasuo; Yonekubo, Ken; Yamagishi, Masaaki; Endo, Itaru;, Assignee: Olympus Optical Co., Ltd. (Tokyo, JP) |
Semiconductor laser
One object of the present invention is to provide a semiconductor laser having a higher efficiency and a lower threshold current than conventional semiconductor lasers. In order to accomplish the obje... Read More
Inventors: Murayama, Yoshimasa; Takeda, Yasutsugu; Nakamura, Michiharu; Shiraki, Yasuhiro; Katayama, Yoshifumi; Chinone, Naoki;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Laser surface treatment method and apparatus for practicing same
An object of the present invention is to provide a surface treatment method capable of treating an object surface so that the surface is provided with high anisotropy, without applying the light to th... Read More
Inventors: Hiraoka, Susumu; Suzuki, Keizo; Nishimatsu, Shigeru;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Sun heat radiation sensor
An aim of the present invention is to provide a relatively cheap device capable of measuring the heat or infrared radiation received from the sun. Typically, but not necessarily exclusively, this info... Read More
Inventors: Rickson, Colin D.;, Assignee: Liquid Crystal Devices Limited (Ruislip, GB) |
Photochromic naphthopyrans
OF THE INVENTION In recent years, photochromic plastic materials, particularly plastic materials for optical applications, have been the subject of considerable attention. In particular, photochromic... Read More
Inventors: Knowles, David B.;, Assignee: Transitions Optical, Inc. (Pinellas Park, FL) |
UV-A, UV-B discrimination sensor
In summarizing the present invention, a first aspect of the present invention relates to a UV-A, UV-B discriminating sensor and which is characterized in the provision of a photochromic layer as the s... Read More
Inventors: Funakoshi, Nobuhiro; Ebisawa, Fumihiro; Hoshino, Mitsutoshi; Yoshida, Takashi; Sukegawa, Ken; Morinaka, Akira; Sashida, Norio; Toeda, Shigeko; Urabe, Miwa;, Assignee: Nippon Telegraph and Telephone Corporation (Tokyo, JP) |
Thin film transistor
It is therefore an object of the present invention to provide a thin film transistor which is free from the above-mentioned defects of the prior art. According to the present invention, the active lay... Read More
Inventors: Ukai, Yasuhiro; Aoki, Shigeo;, Assignee: Hosiden Electronics Co., Ltd. (Osaka, JP) |
Semiconductor device for minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another
OF THE PREFERRED EMBODIMENTS This disclosure of the invention is submitted in furtherance of the constitutional purposes of the Patent Laws "to promote the progress of science and useful arts" (Artic... Read More
Inventors: Chan, Hiang C.; Fazan, Pierre C.; Shih, Bohr-Winn;, Assignee: Micron Technology, Inc. (Boise, ID) |
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Quantum Computing 
