 Continuously integrating high-resolution analog-to-digital converter |
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| Device for the simulation of radar targets in laboratory tests of radar seekers |
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| Overhead rail transportation systems |
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| Modular antenna array |
| In accordance with the invention, an antenna array comprises a plurality of colinear non-parasitic ... |
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| Antenna window cover |
| Referring to FIG. 1, a plan view of a portion of a reentry-type missile in accordance with the ... |
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| High frequency voltage comparator circuit |
| It is therefore an object of the present invention to provide a voltage comparator circuit which ... |
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| Fast analog-digital converter with parallel structure |
| An object of the present invention therefore comprises the making of an analog/digital converter ... |
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| Averaging flash analog-to-digital converter |
| FIG. 1 is a block diagram of a conventional flash-type ADC where an input signal IN is applied to ... |
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A/D converter with a main range up/down counter and a subrange A/D converter
| Details |
Inventors: Moriwaki, Ikuo;
Assignee: Analog Devices KK (Tokyo, JP)
Primary Examiner: Shoop, Jr.; William M.
Assistant Examiner: Williams; H. L.
Attorney, Agent or Firm: Parmelee, Bollinger & Bramblett
A fast, high-resolution A/D converter circuit includes a combination of a main-range up/down counter and a subrange A/D converter. An output from the up/down counter for upper bits is D/A-converted and subtracted from an input signal, and the remainder of subtraction is A/D-converted by the subrange A/D converter, thereby obtaining high-resolution conversion data. The circuit has a feedback loop which detects that the remainder becomes less than LSB of the up/down counter and stops a count operation. By discriminating that the remainder is more/less a predetermined level set higher than the LSB of the counter or outside/inside a predetermined range, a count rate is switched between high and low rates. The remainder enters subrange via the low rate count stage. |
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DETAILED DESCRIPTION It is a primary object of the present invention to provide a fast, high-resolution A/D converter.
It is another object of the present invention to provide an A/D converter not requiring a sample/hold circuit or a comparator at an analog input end.
It is still another object of the present invention to prevent, when an up/down counter is used as a converting element, an LSB of a digital value as a conversion result from fluttering by up/down count.
It is still another object of the present invention to perform, when conversion is divided into a main range and a subrange, conversion in each range by automatic switching on the basis of range detection without alternately, sequentially performing conversion in the respective ranges.
It is still another object of the present invention to achieve a buffer effect so that switching from the main range to the subrange can be smoothly performed.
It is still another object of the present invention to increase a speed of conversion in the main range to improve followability with respect to a large-amplitude input, and to prevent, when conversion in the subrange is to be performed at a middle speed, a mutual interference between conversion results in the two ranges at a boundary region thereof.
It is still another object of the present invention to linearly link the main range and the subrange without processing the data.
It is still another object of the present invention to process, in subrange conversion, a bipolar conversion input by a unipolar converter.
It is still another object of the present invention to simply link, when a bipolar input signal is used, bits of the main range and the subrange without performing data correction.
An A/D converter of the present invention comprises an up/down counter for counting clock pulses to generate upper bits of conversion data, a D/A converter for converting an output from the up/down counter into an analog value, a subtractor for obtaining a remainder between an analog input signal to be converted and an output from the D/A converter, an A/D converter for converting an output from the subtractor into a digital value to generate lower bits to be linked to the upper bits, and count control means for discriminating the polarity and magnitude of the remainder obtained by the subtractor and performing count direction control and count stop control when the difference reaches a range SR for the lower bits
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