Adaptive flash analog/digital converter for differential input signal

DETAILED DESCRIPTION We claim as our invention: 1.
A circuit for converting a differential analog input signal to a coded digital output signal, comprising: a level shifter for shifting the level of said differential input signal with respect to a ground potential; converter means coupled to said level shifter for converting said differential input signal to a single-ended analog signal referenced to said ground potential, said converter means including control means for varying the level of said single-ended analog signal with respect to said ground potential in response to a control signal such that an average value of said single-ended analog signal always corresponds to a zero value of said differential analog input signal; a reference generator for producing a plurality of reference signals between constant upper and lower reference values, one of said reference signals being a midpoint value between said upper and lower values; differencing means coupled to said converter means and to said reference generator for producing a difference signal representing the difference between said single-ended analog signal and said one reference signal having said midpoint value; an average detector coupled to said differencing means and to said converter means for determining and storing an average value of said difference signal, and for producing said control signal representing said average value; comparator means comprising a plurality of individual comparators each receiving said single-ended analog signal and a different one of said reference signals, said comparator means producing simultaneously a plurality of uncoded digital signals representing said shifted analog input signal, at least a particular one of said digital signals always representing a zero value of said differential analog input signal.
2.
The circuit of claim 1, further comprising hold means for disabling said circuit in response to a hold signal.
3.
The circuit of claim 2, wherein said hold means includes a gate for blocking said differential analog input signal