Averaging flash analog-to-digital converter

DETAILED DESCRIPTION FIG.
1 is a block diagram of a conventional flash-type ADC where an input signal IN is applied to a first input terminal of each of 2.
sup.
n -1 comparators 114a to 114z.
A second input terminal of each comparators is coupled to receive a respectively different reference value provided by a resistor ladder which includes first and second sources of reference potential (V+ and ground) and 2.
sup.
n-1 serially connected resistors 112a to 112z.
These resistors are desirably of equal value and are arranged as a voltage divider network such that the reference potential for any comparator is obtained from the junction of two of the resistors 112.
The comparators 114a to 114z amplify the difference between the input signal level and the reference level.
Their output signals are below a predetermined logic threshold whenever the input signal value is greater than the respective reference signal value and is above a logic threshold value whenever the input signal value is less than the respective reference signal value.
The output signals of these comparators are applied to respective latches 116a to 116z.
Each of these latches is responsive to a clock signal CK to store the instantaneous output state of its associated comparator 114a to 114z.
These stored values are applied to a decoder 118.
Decoder 118 which may be a conventional thermometer type decoder, or a priority encoder, generates an n-bit digital output value representing the position in the ladder network of the reference potential which is closest in value to the input signal potential.
That is to say, the number of the comparator highest in the chain which has a logic-high output signal, where the comparator coupled to ground by one reference resistor is number 1 and the comparator coupled to V+ is number 2.
sup.
-1.
For relatively large numbers of bits in the digital output value, this type of ADC may present significant loads to the input signal IN and may be subject to significant integral and differential linearity errors