Circuit for reducing differential nonlinearities in multi-stage digital-to-analog converters

DETAILED DESCRIPTION In the following detailed description and in the several figures of the drawing, like elements are identified with like reference numerals.
Referring now to the block diagram of FIG.
1, shown therein is a digital-to-analog conversion system 100 which includes first and second staged converters 200, 300.
The conversion system 100 converts a digital signal D.
sub.
in which includes a plurality of bits that are grouped into two groups identified as LSW and MSW.
The LSW group corresponds to the least significant bits of the digital signal D.
sub.
in and the MSW group corresponds to the most significant bits of the digital signal D.
sub.
in.
The LSW group is provided to the first converter 200, and the MSW is provided to the second converter 300, which also accepts the output V.
sub.
LW provided by the first converter 200.
The output of the second converter 300 is the output of the digital-to-analog conversion system 100.
To the extent appropriate, the digital conversion system 100 may include more stages, for example, to allow for conversion of a digital signal having a larger number of bits.
For example, the conversion system 100 may have another converter stage which accepts more significant bits than the MSW group and would also accept the analog output provided by the second converter 300.
Staged conversion systems such as that generally depicted in FIG.
1 are known to persons skilled in the art.
As is further known to persons skilled in the art, the output of a lesser weighted stage is coupled to the stage of next greater weight via an LSB element such as a capacitor or resistor (depending on the weighting elements used).
The disclosed invention is directed to a switched capacitor array for use in a staged digital-to-analog conversion system which reduces the differential nonlinearity associated with the coupling LSB elements.
Referring now to the block diagram of FIG.
2, shown therein is a digital-to-analog (D/A) converter 10 which may be used as a stage for converting a group of bits other than the least significant bits in a multi-stage conversion system